Hi

Just to clarify:

“Sub Harmonics” is a term often used to describe spurs at carrier / N
where N is pretty small. If N = 4 you would be looking for spurs at
0.25, 0.5, 0.75, 1.25, 1.5 and 1.75 times the carrier frequency. This
would be a common way to talk about them in the context of “sub
harmonics are 120 db down”.

Indeed if your PLL has a reference at 1/4 the output carrier the same
term might be used. That would be an unusual case, but possible.

In a more conventional PLL, the reference is a (very) small fraction of the
carrier. The term “reference spurs” is typically used to describe them.
They still are at some fraction of the carrier, but the “N” value is quite
large. It is more convienient to look at them as ref x 1, ref x 2 , ref x 3
rather than carrier / 3896.

Typically reference spurs are part of a PLL and sub-harmonics are part
of a multiplier chain. No, it does not have to be that way, but it is how
the terms usually show up.

Again, only trying to clarify what sort of spurs you are chasing.

Bob

Hi Bob,

Thank you for clarifying. On Roland Best's book he states that for some phase detectors there are also subharmonics that will be generated (~ 1/20 reference frequency) but in fact the spurs I'm really interested to estimate are multiple of the reference frequency (i.e. at the input of phase detector). There are a few equations to estimate the reference spurs but I'm chasing the source material.

Regards,
Vasco Soares

-----Original Message-----
From: Bob kb8tq kb8tq@n1k.org
Sent: 6 de fevereiro de 2022 19:08
To: Discussion of precise time and frequency measurement time-nuts@lists.febo.com
Subject: [time-nuts] Re: PLL subharmonic spurs

Hi

Just to clarify:

“Sub Harmonics” is a term often used to describe spurs at carrier / N where N is pretty small. If N = 4 you would be looking for spurs at 0.25, 0.5, 0.75, 1.25, 1.5 and 1.75 times the carrier frequency. This would be a common way to talk about them in the context of “sub harmonics are 120 db down”.

Indeed if your PLL has a reference at 1/4 the output carrier the same term might be used. That would be an unusual case, but possible.

In a more conventional PLL, the reference is a (very) small fraction of the carrier. The term “reference spurs” is typically used to describe them.
They still are at some fraction of the carrier, but the “N” value is quite large. It is more convienient to look at them as ref x 1, ref x 2 , ref x 3 rather than carrier / 3896.

Typically reference spurs are part of a PLL and sub-harmonics are part of a multiplier chain. No, it does not have to be that way, but it is how the terms usually show up.

Again, only trying to clarify what sort of spurs you are chasing.

Bob

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This sounds a little off-topic.

If you are interested in harmonics of the reference frequency at the
input to the phase detector, this will be entirely defined by the
fourier series of the source. Get yourself a 2nd year EE student,
they'll have this info for you.

There will also be harmonics and products generated by the phase
detector inputs, perhaps, since logic gates have to square up rounded
inputs.

depends what sort of phase detector all the way from full linear
multiplier to an XOR gate !

glen

On 7/02/2022 9:27 am, mail@vresearch.pt wrote:

--
Glen English
RF Communications and Electronics Engineer

CORTEX RF

Pacific Media Technologies Pty Ltd trading as Cortex RF

ABN 40 075 532 008

PO Box 5231 Lyneham ACT 2602, Australia.
au mobile : +61 (0)418 975077

Hi

Ok, this is a non-trivially difficult problem. You get into a number of issues
that are very specific to your exact circuit. Often simulation is the most
practical way to work out “what’s what”.

Bob

Just being rude Glen.

I'm searching for a source document that someone could share. Just that.

-----Original Message-----
From: glen english LIST glenlist@cortexrf.com.au
Sent: 6 de fevereiro de 2022 22:51
To: time-nuts@lists.febo.com
Subject: [time-nuts] Re: PLL subharmonic spurs

This sounds a little off-topic.

If you are interested in harmonics of the reference frequency at the input
to the phase detector, this will be entirely defined by the fourier series
of the source. Get yourself a 2nd year EE student, they'll have this info
for you.

There will also be harmonics and products generated by the phase detector
inputs, perhaps, since logic gates have to square up rounded inputs.

depends what sort of phase detector all the way from full linear multiplier
to an XOR gate !

glen

On 7/02/2022 9:27 am, mail@vresearch.pt wrote:

(i.e. at the input of phase detector).

--
Glen English
RF Communications and Electronics Engineer

CORTEX RF

Pacific Media Technologies Pty Ltd trading as Cortex RF

ABN 40 075 532 008

PO Box 5231 Lyneham ACT 2602, Australia.
au mobile : +61 (0)418 975077

time-nuts mailing list -- time-nuts@lists.febo.com -- To unsubscribe send an
email to time-nuts-leave@lists.febo.com
To unsubscribe, go to and follow the instructions there.

On Mon, 7 Feb 2022 09:51:27 +1100
glen english LIST glenlist@cortexrf.com.au wrote:

I do not think that this tone is warranted here.

First of all, nothing about PLL is trivial. Especially not their
non-linear and non-ideal behaviour. I know many EEs who do not fully
understand these, much less have mastered them. Heck, I barely understand
these and I am considered the local PLL-"expert" where I am.
And it gets only worse the more closely one models the parts of a PLL,
most of which are quite far from their usually modeled ideal behaviour.

Second, keep in mind that many people on the time-nuts mailinglist
are hobbyists who came here through various paths. Very few of
those have the mathematical background to read and understand the
textbooks on PLLs, much less to calculate something that is not
in there. Yes, we have quite a few engineers and scientists with
a very high level here. While I do hold these engineers and scientists
to a higher standard and expect them to write mails according to that
level of knowledge and understading, I do not apply that to the majority
on time-nuts. Especially not someone who is new on the list and whose
background is not known. And neither should you.

But back to the topic at hand....

[1] Gives an easy, though probably not very accurate way how to calculate
some of the spurs caused by current leakage.

A more complete analysis, can be found in [2].

For general discussion about PLLs and their behaviour, I would recommend
Best's book [3] (which OP already has) and Gardner [4]. The latter is
quite a bit more theoretical and more complete in its treatment of
PLL behaviour, but also quite a bit harder to apply to a design.

Another book that I quite recommend is [5], written by a TI engineer,
which focuses on the practical aspects of discrete PLL circuit design
and the difficulties faced there. It contains some discussion of spurs,
but I don't remember whether it had a in-depth discussion of the
reference spurs.

Sorry that I can't give a more to the point answer. I haven't looked
into the the spur behaviour of PLL yet and thus have only the most
basic knowlege about it.

		Attila Kinali

[1] "A Simple Method to Accurately Predict PLL Reference Spur Levels
Due to Leakage Current", by Azarian and Ezell, Linear Application Note 143,
2013
https://www.analog.com/media/en/technical-documentation/application-notes/an143f.pdf

[2] "Causes of PLL spurs and their modeling", by Biswas and Bhattacharyya,
2019
https://doi.org/10.1007/s10470-019-01477-z

[3] "Phase-Locked Loops - Design, Simulation and Applications",
by Roland Best, 5th edition 2003

[4] "Phaselock Techniques" by Floyd Gardner, 3rd edition, 2005

[5] "PLL Performance, Simulation, and Design", by Dean Banerjee,
5th edition, 2017
http://www.ti.com/lit/ug/snaa106c/snaa106c.pdf

The driving force behind research is the question: "Why?"
There are things we don't understand and things we always
wonder about. And that's why we do research.
-- Kobayashi Makoto

On 2/7/22 6:05 AM, Attila Kinali wrote:

This is very true. At some trivial level, the output of the phase
detector is some sort of variable duty cycle square wave feeding into a
low pass filter, so a combination of the theoretical spectrum of edges
passed through the filter would get you started.  In any case, it would
tell you where the spurs are likely to be.

However, real PLLs often have other (non-idealized) waveforms going into
the loop filter. A lot have little pulses (charge pump designs), but the
pulses change their size and shape depending on how the PLL is
programmed.  There's also interesting effects if the inputs to the phase
(or phase frequency) detector have harmonic content, or spurious from
other places. It wasn't a PLL, but an ADC, where I had a problem with
the CPU clock rate (at 66 MHz) leaking in to either the power or the
clock a ADC running at a sampling rate of 50MHz. There's a nonlinear
sampling process (just like in a PLL), and small changes in the sampling
instant cause spurs.

Even harder is figuring out what the spur output looks like from the
PLL.  You may have figured out how the spurs look coming out of the loop
filter, but then, that goes into the VCO, and VCOs are hardly paragons
of perfectly linear behavior - they have their own control voltage time
and frequency domain behavior.

to summarize, I think you can get "close" to a decent prediction if
you're using a well known PLL part in a well understood area of
operation. Other than that, you'd best contemplate building a breadboard
or prototype and changing it.  I've got some experience making 7 and 8
GHz signals with the ADF4360, and there are dozens of parameters that
can be adjusted, the results of which are not trivially predictable.  In
our application, we needed to tune a 100 MHz range, and have manageable
spur levels to meet the NTIA/SFCG masks (which are generally -60dBc far
out).

alright then I'll have another go at a more useful response, and I will
provide a reference

Try Floyd Gardiner's  book , "Phaselock Techniques". I have the 3rd
edition in my hand, There is a whole chaptor on phase detectors Chapter
10.  ISBN 978-0-471-43063-6

There is an excellent section on the effect of the PD s-curve on
different applications.

The waveforms input to the phase detector should be tailored to the
particular phase detector in use.

The needs of the phase comparator really are dictated by the needs of
the application- PLL or FLL or both . Sensitivity to harmonics may
actually be desirable... long live the XOR gate !

Example - Harmonic phase (all of them)    may influence a phase
comparator with wide bandwidth much more than one with narrow bandwidth.

• but this may only generate a fixed phase error and this may not bother
  a frequency locked loop.

A double balanced mixer with pure sine wave sources is probably the gold
standard

Horses for courses

On 7/02/2022 9:03 pm, mail@vresearch.pt wrote:

--
Glen English
RF Communications and Electronics Engineer

CORTEX RF

Pacific Media Technologies Pty Ltd trading as Cortex RF

ABN 40 075 532 008

PO Box 5231 Lyneham ACT 2602, Australia.
au mobile : +61 (0)418 975077

Hi

On a lot of PLL’s noise is as much an issue as discrete spikes
( = spurs ). If one widens the definition out to include noise then
things get even more complicated.

Simulation !!! There are free programs out there and “pay” stuff
as well. If you are starting from scratch, they likely will catch a
lot of things you would have missed.

Bob