Hi, I have ip cores that provide an axi-lite interface for control registers, but which do not seem to make timing when that interface is connected to the rfnoc_ctrl clock in an x310 design. I read in the docs that from UHD 4.7 it is possible to define a new module to create this clock, but it isn't clear how to implement this. Is there perhaps an example that someone could share? It would be first prize to generate a global clock that other of my rfnoc blocks could use but I don't want to develop inside the UHD repo itself. Many thanks, Kevin