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Discussion and technical support related to USRP, UHD, RFNoC
View all threadsIs it possible to set sps radio core 1mhz or lower sps without using ddc (RFNOC block)
In RFNOC block i need set sps a muliplay of master clock but not need high
sps. I need low sps but I want to not use any ddc block in my usrp fpga
image? Is it possible ? Can anyone guide me? Thanks in advance
On Tue, May 13, 2025 at 4:34 AM sp stackprogramer@gmail.com wrote:
In RFNOC block i need set sps a muliplay of master clock but not need high
sps. I need low sps but I want to not use any ddc block in my usrp fpga
image? Is it possible ? Can anyone guide me? Thanks in advance
No. The radio sample rates are fixed to the master clock rate.
Any type of sample rate conversion needs to be done digitally. This is
typically done with the DUC or DDC. You could write your own block to do it
if you wanted, but it needs to just do the same thing the DUC or DDC does.
Why can't you use the DDC in your design?
Brian
Thanks for giving useful information. Reason for i want to remove ddc in my
FPGA image core, Really I have a USRP X300, I want to add a custom RFNOC
block that it needs very much resources such a BRAM or others on FPGA USRP
X300. I emphasize I don't afford to buy a new USRP x310 or X400. So I have
to write more optimized code!
On Tue, May 13, 2025 at 4:17 PM Brian Padalino bpadalino@gmail.com wrote:
On Tue, May 13, 2025 at 4:34 AM sp stackprogramer@gmail.com wrote:
In RFNOC block i need set sps a muliplay of master clock but not need
high sps. I need low sps but I want to not use any ddc block in my usrp
fpga image? Is it possible ? Can anyone guide me? Thanks in advance
No. The radio sample rates are fixed to the master clock rate.
Any type of sample rate conversion needs to be done digitally. This is
typically done with the DUC or DDC. You could write your own block to do it
if you wanted, but it needs to just do the same thing the DUC or DDC does.
Why can't you use the DDC in your design?
Brian
On Tue, May 13, 2025 at 10:55 AM sp stackprogramer@gmail.com wrote:
Thanks for giving useful information. Reason for i want to remove ddc in
my FPGA image core, Really I have a USRP X300, I want to add a custom RFNOC
block that it needs very much resources such a BRAM or others on FPGA USRP
X300. I emphasize I don't afford to buy a new USRP x310 or X400. So I have
to write more optimized code!
Understood. You can then remove the DUC or DDC from the design and
implement your own very efficient DUC or DDC in your own block. Just make
sure the interpolation or decimation rate is exactly what you need. For the
X300 it's 200 Msps you're targeting.
Good luck.
Brian
If you only need very simple downsampling/decimation, I think i saw a keep-one-in-n rfnoc block in the repo that only keeps every n-th sample. You might be able to use it, or at least use it as a starting point together with some simple post processing.
It seems like an older block and I have never used it myself so I have no idea if its fully functional on x300, but it probably has a smaller fpga footprint compared to the full ddc block and maybe you can at least use it to get some ideas.
Regards,
Niels
Brian Padalino wrote:
On Tue, May 13, 2025 at 10:55 AM sp stackprogramer@gmail.com wrote:
Thanks for giving useful information. Reason for i want to remove ddc in
my FPGA image core, Really I have a USRP X300, I want to add a custom RFNOC
block that it needs very much resources such a BRAM or others on FPGA USRP
X300. I emphasize I don't afford to buy a new USRP x310 or X400. So I have
to write more optimized code!
Understood. You can then remove the DUC or DDC from the design and
implement your own very efficient DUC or DDC in your own block. Just make
sure the interpolation or decimation rate is exactly what you need. For the
X300 it's 200 Msps you're targeting.
Good luck.
Brian
It can be amazing idea. I will examine it. Thanks for your offer.
On Tue, May 13, 2025 at 7:46 PM niels.steffen.garibaldi--- via USRP-users <
usrp-users@lists.ettus.com> wrote:
If you only need very simple downsampling/decimation, I think i saw a keep-one-in-n
rfnoc block in the repo
https://github.com/EttusResearch/uhd/tree/master/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_keep_one_in_n
that only keeps every n-th sample. You might be able to use it, or at least
use it as a starting point together with some simple post processing.
It seems like an older block and I have never used it myself so I have no
idea if its fully functional on x300, but it probably has a smaller fpga
footprint compared to the full ddc block and maybe you can at least use it
to get some ideas.
Regards,
Niels
Brian Padalino wrote:
On Tue, May 13, 2025 at 10:55 AM sp stackprogramer@gmail.com wrote:
Thanks for giving useful information. Reason for i want to remove ddc in
my FPGA image core, Really I have a USRP X300, I want to add a custom RFNOC
block that it needs very much resources such a BRAM or others on FPGA USRP
X300. I emphasize I don't afford to buy a new USRP x310 or X400. So I have
to write more optimized code!
Understood. You can then remove the DUC or DDC from the design and
implement your own very efficient DUC or DDC in your own block. Just make
sure the interpolation or decimation rate is exactly what you need. For the
X300 it's 200 Msps you're targeting.
Good luck.
Brian
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