usrp-users@lists.ettus.com

Discussion and technical support related to USRP, UHD, RFNoC

View all threads

axi_mm io_signature issue

BP
Brian Padalino
Tue, Mar 11, 2025 11:10 PM

I am checking the IO signatures, and I am seeing that the axi_mm interface
generated in rfnoc_image_core.sv is a bit wonky. I traced it back to the
io_signature.yaml definition here:

https://github.com/EttusResearch/uhd/blob/0dede88c6535ae6ffb30b162c83dc01d59d3bfa0/host/include/uhd/rfnoc/core/io_signatures.yml#L63

It states that it's up to 512-bit, 8 channels, and 48-bit address - but the
m_axi_wdata  and m_axi_rdata is 4192 bits. I think it should be 4096 bits
(512*8) but really I think this should follow some parameters that are
passed into it? Similar to how the radio interface is defined?

Alternatively, the x4xx_core.v file seems to utilise the localparam
DRAM_PORTS_PER_BANK - could the IO signature just use a generic like that?

https://github.com/EttusResearch/uhd/blob/0dede88c6535ae6ffb30b162c83dc01d59d3bfa0/fpga/usrp3/top/x400/x4xx_core.v#L576

Was this just an oversight or is there a plan to "right-size" this
interface based on the parameters passed into it?

Thanks,
Brian

I am checking the IO signatures, and I am seeing that the axi_mm interface generated in rfnoc_image_core.sv is a bit wonky. I traced it back to the io_signature.yaml definition here: https://github.com/EttusResearch/uhd/blob/0dede88c6535ae6ffb30b162c83dc01d59d3bfa0/host/include/uhd/rfnoc/core/io_signatures.yml#L63 It states that it's up to 512-bit, 8 channels, and 48-bit address - but the m_axi_wdata and m_axi_rdata is 4192 bits. I think it should be 4096 bits (512*8) but really I think this should follow some parameters that are passed into it? Similar to how the radio interface is defined? Alternatively, the x4xx_core.v file seems to utilise the localparam DRAM_PORTS_PER_BANK - could the IO signature just use a generic like that? https://github.com/EttusResearch/uhd/blob/0dede88c6535ae6ffb30b162c83dc01d59d3bfa0/fpga/usrp3/top/x400/x4xx_core.v#L576 Was this just an oversight or is there a plan to "right-size" this interface based on the parameters passed into it? Thanks, Brian
WF
Wade Fife
Fri, Mar 14, 2025 12:33 AM

Hi Brian,

I'm pretty sure that's a typo. Someone mixed 4096 with 8192. But it should
not matter as long as the bus is big enough. The extra bits will be ignored
and optimized out. Even 4096 is bigger than needed in most cases.

There has been some work to have the image builder set these widths to
exactly the right size, but it looks like that hasn't been done for the
DRAM interface yet.

Thanks,

Wade

On Tue, Mar 11, 2025 at 6:10 PM Brian Padalino bpadalino@gmail.com wrote:

I am checking the IO signatures, and I am seeing that the axi_mm interface
generated in rfnoc_image_core.sv is a bit wonky. I traced it back to the
io_signature.yaml definition here:

https://github.com/EttusResearch/uhd/blob/0dede88c6535ae6ffb30b162c83dc01d59d3bfa0/host/include/uhd/rfnoc/core/io_signatures.yml#L63

It states that it's up to 512-bit, 8 channels, and 48-bit address - but
the m_axi_wdata  and m_axi_rdata is 4192 bits. I think it should be 4096
bits (512*8) but really I think this should follow some parameters that are
passed into it? Similar to how the radio interface is defined?

Alternatively, the x4xx_core.v file seems to utilise the localparam
DRAM_PORTS_PER_BANK - could the IO signature just use a generic like that?

https://github.com/EttusResearch/uhd/blob/0dede88c6535ae6ffb30b162c83dc01d59d3bfa0/fpga/usrp3/top/x400/x4xx_core.v#L576

Was this just an oversight or is there a plan to "right-size" this
interface based on the parameters passed into it?

Thanks,
Brian


USRP-users mailing list -- usrp-users@lists.ettus.com
To unsubscribe send an email to usrp-users-leave@lists.ettus.com

Hi Brian, I'm pretty sure that's a typo. Someone mixed 4096 with 8192. But it should not matter as long as the bus is big enough. The extra bits will be ignored and optimized out. Even 4096 is bigger than needed in most cases. There has been some work to have the image builder set these widths to exactly the right size, but it looks like that hasn't been done for the DRAM interface yet. Thanks, Wade On Tue, Mar 11, 2025 at 6:10 PM Brian Padalino <bpadalino@gmail.com> wrote: > I am checking the IO signatures, and I am seeing that the axi_mm interface > generated in rfnoc_image_core.sv is a bit wonky. I traced it back to the > io_signature.yaml definition here: > > > https://github.com/EttusResearch/uhd/blob/0dede88c6535ae6ffb30b162c83dc01d59d3bfa0/host/include/uhd/rfnoc/core/io_signatures.yml#L63 > > It states that it's up to 512-bit, 8 channels, and 48-bit address - but > the m_axi_wdata and m_axi_rdata is 4192 bits. I think it should be 4096 > bits (512*8) but really I think this should follow some parameters that are > passed into it? Similar to how the radio interface is defined? > > Alternatively, the x4xx_core.v file seems to utilise the localparam > DRAM_PORTS_PER_BANK - could the IO signature just use a generic like that? > > > https://github.com/EttusResearch/uhd/blob/0dede88c6535ae6ffb30b162c83dc01d59d3bfa0/fpga/usrp3/top/x400/x4xx_core.v#L576 > > Was this just an oversight or is there a plan to "right-size" this > interface based on the parameters passed into it? > > Thanks, > Brian > _______________________________________________ > USRP-users mailing list -- usrp-users@lists.ettus.com > To unsubscribe send an email to usrp-users-leave@lists.ettus.com >