The contents of the latest issue of: International Journal of Embedded and Real-Time Communication Systems (IJERTCS) Official Publication of the Information Resources Management Association Volume 1, Issue 4, October-December 2010 Published: Quarterly in Print and Electronically ISSN: 1947-3176 EISSN: 1947-3184 Published by IGI Publishing, Hershey-New York, USA www.igi-global.com/ijertcs Editor-in-Chief: Seppo Virtanen, University of Turku, Finland GUEST EDITORIAL PREFACE System-on-Chip for Embedded Communication Systems, Part II Jari Nurmi, Tampere University of Technology, Finland To view the editorial preface, please click on the link below. http://igi-global.com/Bookstore/TitleDetails.aspx?TitleId=47449 PAPER ONE A Multidimensional Software Cache for Scratchpad-Based Systems Arnaldo Azevedo (Delft University of Technology, The Netherlands) Ben Juurlink (Technische Universität Berlin, Germany) In many kernels of multimedia applications, the working set is predictable, making it possible to schedule the data transfers before the computation. Many other kernels, however, process data that is known just before it is needed or have working sets that do not fit in the scratchpad memory. Furthermore, multimedia kernels often access two or higher dimensional data structures and conventional software caches have difficulties to exploit the data locality exhibited by these kernels. For such kernels, the authors present a Multidimensional Software Cache (MDSC), which stores 1- 4 dimensional blocks to mimic in cache the organization of the data structure. Furthermore, it indexes the cache using the matrix indices rather than linear memory addresses. MDSC also makes use of the lower overhead of Direct Memory Access (DMA) list transfers and allows exploiting known data access patterns to reduce the number of accesses to the cache. The MDSC is evaluated using GLCM, providing an 8% performance improvement compared to the IBM software cache. For MC, several optimizations are presented that reduce the number of accesses to the MDSC. To obtain a copy of the entire article, click on the link below. http://igi-global.com/Bookstore/Article.aspx?TitleId=47539 PAPER TWO Joint Uplink and Downlink Performance Profiling of LTE Protocol Processing on a Mobile Platform David Szczesny (Ruhr-Universität Bochum, Germany) Sebastian Hessel (Ruhr-Universität Bochum, Germany) Anas Showk (Ruhr-Universität Bochum, Germany) Attila Bilgic (Ruhr-Universität Bochum, Germany) Uwe Hildebrand (Comneon GmbH, Germany) Valerio Frascolla (Comneon GmbH, Germany) This article provides a detailed profiling of the layer 2 (L2) protocol processing for 3G successor Long Term Evolution (LTE). For this purpose, the most processing intensive part of the LTE L2 data plane is executed on top of a virtual ARM based mobile phone platform. The authors measure the execution times as well as the maximum data rates at different system setups. The profiling is done for uplink (UL) and downlink (DL) directions separately as well as in a joint UL and DL scenario. As a result, the authors identify time critical algorithms in the protocol stack and check to what extent state-of-the-art hardware platforms with a single-core processor and traditional hardware acceleration concepts are still applicable for protocol processing in LTE and beyond LTE mobile devices. To obtain a copy of the entire article, click on the link below. http://igi-global.com/Bookstore/Article.aspx?TitleId=47540 PAPER THREE Performance Analysis of On-Chip Communication Structures under Device Variability Faiz-ul Hassan (University of Glasgow, UK) Wim Vanderbauwhede (University of Glasgow, UK) On-chip communication is becoming an important bottleneck in the design and operation of high performance systems where it has to face additional challenges due to device variability. Communication structures such as tapered buffer drivers, interconnects, repeaters, and data storage elements are vulnerable to variability, which can limit the performance of the on-chip communication networks. In this regard, it becomes important to have a complete understanding of the impact that variability will have on the performance of these circuit elements in order to design high yield and reliable systems. In this paper, the authors have characterized the performance of the communication structures under the impact of random dopant fluctuation (RDF) for the future technology generations of 25, 18, and 13 nm. For accurate characterization of their performance, a Monte Carlo simulation method has been used along with predictive device models for the given technologies. Analytical models have been developed for the link failure probability of a repeater inserted interconnect which uses characterization data of all communication structures to give an accurate prediction of the link failure probability. The model has also been extended to calculate the link failure probability of a wider communication link. To obtain a copy of the entire article, click on the link below. http://igi-global.com/Bookstore/Article.aspx?TitleId=47541 ***************************************************** For full copies of the above articles, check for this issue of the International Journal of Embedded and Real-Time Communication Systems (IJERTCS) in your institution's library. This journal is also included in the IGI Global aggregated "InfoSci-Journals" database: http://www.igi-global.com/EResources/InfoSciJournals.aspx. ***************************************************** CALL FOR PAPERS Mission of IJERTCS: The mission of the International Journal of Embedded and Real-Time Communication Systems (IJERTCS) is to disseminate recent advancements and innovations in this interdisciplinary research area for field researchers, practitioners, scientists, academicians, students, and IT professionals. IJERTCS focuses on overcoming challenges involved in the rapid development of embedded communication systems towards feature-rich multimedia computers. Coverage of IJERTCS: The International Journal of Embedded and Real-Time Communication Systems (IJERTCS) extensively covers research in the area of embedded and real-time communication systems. Within this field, topics to be discussed in the journal include (but are not limited to) the following: Asynchronous and synchronous circuit techniques Design methods Embedded networks (built-in networks in embedded communication devices) Emerging new topics Fault-tolerant hardware and software technologies Formal design and verification methods Hardware and software solutions for protocol processing Hardware and software solutions for real-time systems Hardware platforms and technologies Hardware/software co-design Modeling and verification methods On-chip communication in SoC and NoC OWA (open wireless architecture) Performance modeling Platform based design Real-time computing Reconfigurable systems Security issues and technologies Single-chip SDR (software defined radio) solutions Software design Testing techniques Interested authors should consult the journal's manuscript submission guidelines at www.igi-global.com/ijertcs All inquiries and submissions should be sent to: Editor-in-Chief: Seppo Virtanen at seppo.virtanen@utu.fi