Hi,
El 19/08/2011 00:28, Tijd Dingen escribió:
Generally speaking, any ADC approach that uses /affordable/ ADC's (read: no GHz sampling rates) will result in lower number of timestamps per second than with the TDC in fpga approach.
I know, I know :) As I said, first I'm looking around the different
techniques, advantages, disadvantages... I would like to know if the ADC
approach has other advantages
So if you only have to timestamp at a moderate rate, then the adc could very well suit your needs. If you want to do continuous timestamping at a high rate then the adc approach doesn't cut it. Or if it can, I'd be interested in some good reading material about that...
My main current application is jitter measurement and characterization,
so a moderate rate could be enough (but the greater the rate, the
better, of course :) ), but I prefer in this case, higher precission
more than higher rate.
Besides with the fpga approach it is solve problem once, instantiate many times == multi-channel TDC for a nice price.
Of course :)
Regards,
Javier
--
Javier Herrero
Chief Technology Officer EMAIL: jherrero@hvsistemas.com
HV Sistemas S.L. PHONE: +34 949 336 806
Los Charcones, 17 FAX: +34 949 336 792
19170 El Casar - Guadalajara - Spain WEB: http://www.hvsistemas.com
Hi,
El 19/08/2011 00:28, Tijd Dingen escribió:
>
> Generally speaking, any ADC approach that uses /affordable/ ADC's (read: no GHz sampling rates) will result in lower number of timestamps per second than with the TDC in fpga approach.
I know, I know :) As I said, first I'm looking around the different
techniques, advantages, disadvantages... I would like to know if the ADC
approach has other advantages
>
>
> So if you only have to timestamp at a moderate rate, then the adc could very well suit your needs. If you want to do continuous timestamping at a high rate then the adc approach doesn't cut it. Or if it can, I'd be interested in some good reading material about that...
>
My main current application is jitter measurement and characterization,
so a moderate rate could be enough (but the greater the rate, the
better, of course :) ), but I prefer in this case, higher precission
more than higher rate.
> Besides with the fpga approach it is solve problem once, instantiate many times == multi-channel TDC for a nice price.
Of course :)
Regards,
Javier
--
------------------------------------------------------------------------
Javier Herrero
Chief Technology Officer EMAIL: jherrero@hvsistemas.com
HV Sistemas S.L. PHONE: +34 949 336 806
Los Charcones, 17 FAX: +34 949 336 792
19170 El Casar - Guadalajara - Spain WEB: http://www.hvsistemas.com
