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View all threadsRe: X310 clock signal for aliasing (BasicRX daughter board)
My understanding is that the clock signal fed to the daughter-cards
is typically some fraction of the master_clock
frequency, and is designed to provide a REF signal for
synthesizers, etc. It should be synchronized to the
ADC clocks, but won't necessarily be at the same frequency.
I have further investigated and I see
1/ a clear clock signal between GND and clk_p (J38 pin 2
on https://files.ettus.com/schematics/basic_dbs/BasicRX.pdf)
of the BasicRX board for about 1-s when the USRP Source Block in
GNU Radio Companion displays
[INFO] [X300] Radio 1x clock: 200 MHz
but then the signal vanishes
2/ I can change this short clock signal frequency by providing the
argument dboard_clock_rate to the USRP Source Block: I have checked
that the default frequency is 100 MHz, I can request 50 MHz and RFNOC
somewhat complains when requesting 200 MHz but still the clock signal
is visible for a second.
so this signal can be controlled from software. Is there a way to keep
the signal as the flowgraph is running rather than only a second or so
at startup?
Thanks
--
JM Friedt, FEMTO-ST Time & Frequency, 26 rue de l'Epitaphe, 25000
Besancon, France
On 08/01/2025 01:47, friedtj@free.fr wrote:
My understanding is that the clock signal fed to the daughter-cards
is typically some fraction of the master_clock
frequency, and is designed to provide a REF signal for
synthesizers, etc. It should be synchronized to the
ADC clocks, but won't necessarily be at the same frequency.
I have further investigated and I see
1/ a clear clock signal between GND and clk_p (J38 pin 2
on https://files.ettus.com/schematics/basic_dbs/BasicRX.pdf)
of the BasicRX board for about 1-s when the USRP Source Block in
GNU Radio Companion displays
[INFO] [X300] Radio 1x clock: 200 MHz
but then the signal vanishes
2/ I can change this short clock signal frequency by providing the
argument dboard_clock_rate to the USRP Source Block: I have checked
that the default frequency is 100 MHz, I can request 50 MHz and RFNOC
somewhat complains when requesting 200 MHz but still the clock signal
is visible for a second.
so this signal can be controlled from software. Is there a way to keep
the signal as the flowgraph is running rather than only a second or so
at startup?
Thanks
My guess is that the basic_rx host-side driver turns it off, because the
basic_rx doesn't actually use it, so it would be floating, and
thus potentially radiating and causing an issue at both the
fundamental and odd harmonics.
Hopefully "last" question:
I have set
this->get_iface()->set_clock_enabled(dboard_iface::UNIT_RX, false);
to true and surely enough I get a continuous clock on the clk_p pin
(J38 pin 2 of https://files.ettus.com/schematics/basic_dbs/BasicRX.pdf)
which looks like an unbalanced signal since I probe from an oscilloscope
referenced to ground.
However the output signal frequency
1/ appears very unstable (arguably from an oscilloscope trace frequency
measurement), varying by several MHz around a mean value
2/ the mean value is not the one set with "dboard_clock_rate=" even though
this->get_iface()->get_clock_rate(dboard_iface::UNIT_RX);
properly returns the value programmed with this argument. When setting
dboard_clock_rate to 200 MHz, the oscilloscope reads something between
160 and 170 MHz, when setting to 100 MHz the frequency reads 85 to 88 MHz,
and when setting to 50 MHz the reading is 42 - 44 MHz.
I thought maybe the master clock setting would be incorrect but 1/ libuhd
returns 200 MHz master clock and 2/ a value of 184.32 MHz would not match
the observations anyway.
I have read the source code of the other boards enabling set_clock_enabled()
(e.g. db_tvrx.cpp or twinrx_ctrl.cpp) and neither seems to set any other parameter
than _db_iface->set_clock_enabled(dboard_iface::UNIT_TX, true);
Am I missing some additional initialization step? PLL locking condition?
Thanks
Forget this email please ... I just need to learn how to use a digital oscilloscope.
Aliasing error, all working very well, output clock is at the desired frequency.
----- Mail original -----
De: "friedtj" friedtj@free.fr
À: "usrp-users" usrp-users@lists.ettus.com
Envoyé: Mercredi 8 Janvier 2025 14:19:29
Objet: [USRP-users] Re: X310 clock signal for aliasing (BasicRX daughter board)
Hopefully "last" question:
I have set
this->get_iface()->set_clock_enabled(dboard_iface::UNIT_RX, false);
to true and surely enough I get a continuous clock on the clk_p pin
(J38 pin 2 of https://files.ettus.com/schematics/basic_dbs/BasicRX.pdf)
which looks like an unbalanced signal since I probe from an oscilloscope
referenced to ground.
However the output signal frequency
1/ appears very unstable (arguably from an oscilloscope trace frequency
measurement), varying by several MHz around a mean value
2/ the mean value is not the one set with "dboard_clock_rate=" even though
this->get_iface()->get_clock_rate(dboard_iface::UNIT_RX);
properly returns the value programmed with this argument. When setting
dboard_clock_rate to 200 MHz, the oscilloscope reads something between
160 and 170 MHz, when setting to 100 MHz the frequency reads 85 to 88 MHz,
and when setting to 50 MHz the reading is 42 - 44 MHz.
I thought maybe the master clock setting would be incorrect but 1/ libuhd
returns 200 MHz master clock and 2/ a value of 184.32 MHz would not match
the observations anyway.
I have read the source code of the other boards enabling set_clock_enabled()
(e.g. db_tvrx.cpp or twinrx_ctrl.cpp) and neither seems to set any other parameter
than _db_iface->set_clock_enabled(dboard_iface::UNIT_TX, true);
Am I missing some additional initialization step? PLL locking condition?
Thanks
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