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Fwd: Re: Frequency Stability of Trimble Mini-T

H
hasweb@has.org.nz
Thu, Oct 16, 2008 11:05 PM

----- Forwarded message from hasweb@has.org.nz -----
Date: Fri, 17 Oct 2008 12:02:48 +1300
From: hasweb@has.org.nz
Reply-To: hasweb@has.org.nz
Subject: Re: [time-nuts] Frequency Stability of Trimble Mini-T
To: Mike Monett XDE-L2G3@myamail.com

Quoting Mike Monett XDE-L2G3@myamail.com:

"Lux, James P" james.p.lux@jpl.nasa.gov wrote:

[...]

Even without  TMR  or other similar  schemes,  the  probability of
upset IS  pretty low. However, as Black or Scholes  said  (I can't
remember which), "One should not confuse very low probability with
impossible". If it absolutely, positively can't take any hit, then
some more work is involved.

James Lux, P.E.

How do you do that? Any web links to study?

As far  as I know, it is impossible to absolutely  guarantee against
metastability. Do you wait a week for the metastability to settle?

If zero probability of failure is so important, you would  also have
to include  the  probability of a solder joint  opening,  or  a chip
failing due  to metal migration or latent ESD damage. That  is never
zero.

Of course, after the system is perfect, someone will take it and put
it on a destroyer running Windows:)

Best Regards,

Mike Monett


Mike

You could always look at: United States Patent US4820939.
But dont bet on it.

Bruce

----- End forwarded message -----

----- Forwarded message from hasweb@has.org.nz ----- Date: Fri, 17 Oct 2008 12:02:48 +1300 From: hasweb@has.org.nz Reply-To: hasweb@has.org.nz Subject: Re: [time-nuts] Frequency Stability of Trimble Mini-T To: Mike Monett <XDE-L2G3@myamail.com> Quoting Mike Monett <XDE-L2G3@myamail.com>: > "Lux, James P" <james.p.lux@jpl.nasa.gov> wrote: > > [...] > > > Even without TMR or other similar schemes, the probability of > > upset IS pretty low. However, as Black or Scholes said (I can't > > remember which), "One should not confuse very low probability with > > impossible". If it absolutely, positively can't take any hit, then > > some more work is involved. > > > James Lux, P.E. > > How do you do that? Any web links to study? > > As far as I know, it is impossible to absolutely guarantee against > metastability. Do you wait a week for the metastability to settle? > > If zero probability of failure is so important, you would also have > to include the probability of a solder joint opening, or a chip > failing due to metal migration or latent ESD damage. That is never > zero. > > Of course, after the system is perfect, someone will take it and put > it on a destroyer running Windows:) > > Best Regards, > > Mike Monett > > _______________________________________________ > Mike You could always look at: United States Patent US4820939. But dont bet on it. Bruce ----- End forwarded message -----
MM
Mike Monett
Fri, Oct 17, 2008 12:05 AM

Mike

You could always look at: United States Patent US4820939.

But dont bet on it.

Bruce

There's lots of them. I don't believe them.

Philips even  has  one on their 74F50729:  US5,789,945.  I  have not
tried it but some reports say it doesn't work.

OTOH, I used the digital mixer described previously to lock as close
to the  metastability  condition of a flip-flop as  possible  for my
second patent.

The circuit  tried to lock on logic level 0.5, but  of  course could
never accomplish  this task. But this tied the edge of a delay  to a
reference so I could measure the offset and window width in the data
separator with a TIA.

The circuit  used Motorola MECL 10KH ECL. I could  see  the attached
waveforms on  my  Tek 7104 fairly often. It was  barely  possible to
measure the  jitter  between the clock and d inputs with  a  HP 5370
TIA. I don't remember the value but it was quite small.

Later I  upgraded to Motorola EclInPs. Using the  same  circuit, and
others like it, I could no longer get any metastability condition on
a MC100EP52 D flop no matter how hard I tried.

So the faster chips really are difficult to get into a metastability
condition. But  I continue to use cascaded shift  registers  to keep
them at bay.

Best Regards,

Mike Monett

hasweb@has.org.nz wrote: >Mike > You could always look at: United States Patent US4820939. > But dont bet on it. >Bruce There's lots of them. I don't believe them. Philips even has one on their 74F50729: US5,789,945. I have not tried it but some reports say it doesn't work. OTOH, I used the digital mixer described previously to lock as close to the metastability condition of a flip-flop as possible for my second patent. The circuit tried to lock on logic level 0.5, but of course could never accomplish this task. But this tied the edge of a delay to a reference so I could measure the offset and window width in the data separator with a TIA. The circuit used Motorola MECL 10KH ECL. I could see the attached waveforms on my Tek 7104 fairly often. It was barely possible to measure the jitter between the clock and d inputs with a HP 5370 TIA. I don't remember the value but it was quite small. Later I upgraded to Motorola EclInPs. Using the same circuit, and others like it, I could no longer get any metastability condition on a MC100EP52 D flop no matter how hard I tried. So the faster chips really are difficult to get into a metastability condition. But I continue to use cascaded shift registers to keep them at bay. Best Regards, Mike Monett
HM
Hal Murray
Fri, Oct 17, 2008 5:33 PM

You could always look at: United States Patent US4820939.
But dont bet on it.

I'd go so far as to suggest betting against it.

Back in the 80s when word about metastability was reaching trade rags and
real designers, I went to a trade show that had a panel on it.  One guy got
it totally wrong.  1 or 2 mumbled and didn't contribute much.  The only guy
who got it right was John Wakerly from Stanford.  (Of course, maybe I drunk
his cool-aid and not theirs.)

Back in those days, there was a lot of activity in designing kludgey circuits
to "fix" metastability.  I could usually find the flaw.  It got boring after
a while.  The classic was a circuit to detect metastability and reset the FF.
That reset signal would sometimes have runt pulses.

There are several problems with such kludges.  First is that they don't work.
Second is that they usually make things worse by adding logic in the
critical path thus reducing the settling time.  On top of that, they are
usually a pain to analyze.  (If the designer analyzed them correctly, he
would have thrown it out.)

It's much better to keep the circuit simple.  Then you have a chance of
correctly estimating the MTTF.

The key is settling time.

The best analog of metastability that I know of is rolling a ball over a
speed bump.  If the ball is slow, it bounces back.  If the ball is fast, it
goes up and over.  If the speed is just right, the ball gets to the top of
the bump and stalls.  If you have a frictionless bump and such, the ball will
eventually fall off one side or the other.  (You can't adjust the speed to
the exact value.)

Johnson and Graham's book on Black Magic has a good section on metastability.
I think there are some good scope pictures, but my copy isn't handy.

I used to use metastability as a calibration on logic design books.  If I
couldn't find metastability or synchronizer in the index I didn't expect
much.  If I did find something, I would scan that section.  A lot of them
weren't very good.

--
These are my opinions, not necessarily my employer's.  I hate spam.

> You could always look at: United States Patent US4820939. > But dont bet on it. I'd go so far as to suggest betting against it. Back in the 80s when word about metastability was reaching trade rags and real designers, I went to a trade show that had a panel on it. One guy got it totally wrong. 1 or 2 mumbled and didn't contribute much. The only guy who got it right was John Wakerly from Stanford. (Of course, maybe I drunk his cool-aid and not theirs.) Back in those days, there was a lot of activity in designing kludgey circuits to "fix" metastability. I could usually find the flaw. It got boring after a while. The classic was a circuit to detect metastability and reset the FF. That reset signal would sometimes have runt pulses. There are several problems with such kludges. First is that they don't work. Second is that they usually make things worse by adding logic in the critical path thus reducing the settling time. On top of that, they are usually a pain to analyze. (If the designer analyzed them correctly, he would have thrown it out.) It's much better to keep the circuit simple. Then you have a chance of correctly estimating the MTTF. The key is settling time. The best analog of metastability that I know of is rolling a ball over a speed bump. If the ball is slow, it bounces back. If the ball is fast, it goes up and over. If the speed is just right, the ball gets to the top of the bump and stalls. If you have a frictionless bump and such, the ball will eventually fall off one side or the other. (You can't adjust the speed to the exact value.) Johnson and Graham's book on Black Magic has a good section on metastability. I think there are some good scope pictures, but my copy isn't handy. I used to use metastability as a calibration on logic design books. If I couldn't find metastability or synchronizer in the index I didn't expect much. If I did find something, I would scan that section. A lot of them weren't very good. -- These are my opinions, not necessarily my employer's. I hate spam.