Dear Li Ang,

Nice to have you back reporting on your progress!

Now, you have some pretty impressive performance going on there. Looks
like a nice little unit too.

Is the C-channel the SMA on the back of the PCB?

How did you wire up the 74LVC2G14?

While it is tempting to use both channels in it, don't if you want to
keep cross-talk between channels low.

Cheers,
Magnus

On 02/23/2015 02:10 PM, Li Ang wrote:

Hi Magnus,
The C channel is the SMA on the back of the PCB. The input of 74LVC2G14
is set to 0.5vcc with 1k resistor and AC coupled with 100nF.
Today I compared the performance 74LVC2G04, 74LVC2G17, 74LVC2G14.
http://www.qsl.net/b/bi7lnq//freqcntv4.1/test/20150224/  .
I saw people talking about using 74AC to square the signal, what's the
difference between 74LVC and 74AC? 74AC is not easy to get.

Thanks

Li Ang

2015-02-24 5:36 GMT+08:00 Magnus Danielson magnus@rubidium.dyndns.org:

On Mon, 23 Feb 2015 21:10:30 +0800
"Li Ang" 379998@qq.com wrote:

Thanks for the update!

Yes. You should not use a logic gates with analog input signals.
Using a 74LVC14 helps due to its Schmitt-Trigger input. I think
the proper solution here would be to use a high speed comparator
instead (with hysteresis).

Do you have an Idea why the ADEV diverges between 10s and 100s?
Are those temperature effects on the different input configurations?
Or is it an artefact of the measurement?

		Attila Kinali

--
It is upon moral qualities that a society is ultimately founded. All
the prosperity and technological sophistication in the world is of no
use without that foundation.
-- Miss Matheson, The Diamond Age, Neil Stephenson

On Tue, 24 Feb 2015 14:43:10 +0800
Li Ang lllaaa@gmail.com wrote:

These are different families of chip production. You can see the 74HCxx as
the grandfather, 74ACxx as the father and the 74LVCxx as the son.

IIRC the AC (Advanced CMOS) was introduced in the 80s. The process
which they were produced got superseeded and also the voltage levels
went down. The LVC (Low Voltage CMOS) and LVX families are the current
choice for logic gates. The main difference is that the node size (those nm
measures people boast with, when they talk about chips these days) went
down and with that the threshold voltage of the FETs and the maximum
voltage the chips can withstand. Of course there are differences in the
timing specs as well.

TI's Logic Guide[1] and their Logic Migration Guide[2] contain
additional information.

			Attila Kinali

[1] http://www.ti.com/lit/sg/sdyu001aa/sdyu001aa.pdf
[2] http://www.ti.com/lit/ml/scyb032/scyb032.pdf

--
It is upon moral qualities that a society is ultimately founded. All
the prosperity and technological sophistication in the world is of no
use without that foundation.
-- Miss Matheson, The Diamond Age, Neil Stephenson

Attila wrote:

See below for three possibilities, in addition to the Wenzel-style
squarer I posted previously.

Circuit A is the simplest of these (and, in my view, best, because it
minimizes noise).  It is DC-coupled (although, if the input may have
a DC offset, you should add a 10n coupling cap before R2).  The
LT1719 uses separate supplies for the front end and the output, so
you can run the input on split +/- 5v supplies and still have
whatever logic level you want.  The down side is that you need +5v
and -5v supplies, which you may not already have.  Still, I think it
is better to add these supplies than to try to do the whole
conversion with only a 3v supply, because (i) these comparators work
better on 5v than on 3v, and (ii) with 3v supplies you have to be
very careful with the input level so as not to exceed the allowable
input voltage.

Circuit B uses the simple-to-apply LT1720 in an AC-coupled
circuit.  Again, it uses a 5v supply (but no -5v supply) for the
reasons given above.  Use your favorite 5v to 3v logic converter, or
just put a 220 ohm (series) and 330 ohm (shunt) resistive divider on
the output to drive 3v logic.

Circuit C allows using the LT1720 with the existing 3v supply, at the
cost of adding an input transformer.  This connection keeps the input
voltage within the comparator's allowable input voltage range.

Any of these should work better than a logic gate.

Best regards,

Charles

Hi Attila
Thanks for the history about 74 series.
BTW, The result.gif is a TDEV chart. I only know that different K means
different kinds of noise. I don't know what it means if the turnning corner
comes earlier or latter.

Hi Charles
Thanks for the circuit. I have some LT1016 in hand, I will evaluate with
it.

2015-02-25 0:02 GMT+08:00 Attila Kinali attila@kinali.ch:

Magnus wrote:

A 1 Vrms, 10MHz sine wave has a zero-cross slew rate of 88v/uS
(88mV/nS).  One would think that would be enough to avoid indecision
in a comparator with 5-10nS of propagation delay.  However, the
LT1016 (10nS) is prone to jitter problems when operating as a ZCD
with such a signal, and external hysteresis does not help much
because it is delayed by 10nS.  (The problem appears to be that the
front end has some indecision at this input slew rate that happens
faster than the propagation delay to the output -- but this is just
an inference because the internal nodes are not accessible for
measurement.)  For this application, the small amount of internal
hysteresis of the LT1719 and LT1720 is very beneficial.

Best regards,

Charles

Hi
Thanks about the explanation on hysteresis and comparator.
The PM6685(http://assets.fluke.com/manuals/PM6685__smeng0000.pdf )
is using 74ALS176 as the frontend for REF channel.
So
I tried that on the previous board. The performance is better with
74ALS176+74LVC2G14 than MC100LVELT22 at the sin wave input condition.
Since the stdev has reached the spec of TDC chip, I need to do
some more experiments with these chips next.
There are some questions I want to ask:

1. Does the trigger interval need to be very accurate? Now I am using
   software scheduler to generate the interval, it might vary few ms.
2. Does any one have the test data of 12 digit/s counter when DUT=REF?
   I want to know the gap between mine and a  commercial counter.

Thanks

Li Ang

2015-02-27 4:30 GMT+08:00 Charles Steinmetz csteinmetz@yandex.com:

I did a lot of testing of 53132A counters a while back to research how well the interpolators worked and to measure the interference when CH1 gets too close to CH2. There was some discussion on the list about this at the time.

For the context, see: https://www.febo.com/pipermail/time-nuts/2014-April/084670.html
For the plots, see: http://leapsecond.com/pages/53132/

A good paper to read about the trouble when DUT is close (or "equal" to REF) is:
http://literature.cdn.keysight.com/litweb/pdf/5990-9189EN.pdf
"Isolating Frequency Measurement Error and Sourcing Frequency Error near the Reference Frequency Harmonics"

See also: https://www.febo.com/pipermail/time-nuts/2012-October/070737.html

/tvb

Tom,

On 02/27/2015 01:18 PM, Tom Van Baak wrote:

Nice reading and illustration of the problem. It does not go into
explain where these errors come from.

I especially like that he worked on an offset frequency to handle source
issues and that he elaborates with both time-base time and frequency
offset, as well as average and peak-to-peak values.

Have you seen any papers going into depth about that?

Enrico have been looking at post-processing filtering, and it's effects.

I just haven't seen any paper giving much about how cross-talk and such
affects non-linearity and post-processing such as frequency reading and
ADEV. I have my own model from experience and various sources, but not
seen anything comprehensive.

Cheers,
Magnus

The Robert Leiby (5990-9189EN) paper was a real find. Agilent sent it to me after I ran tests of their new 53230A counter. I had two of them on loan (TCXO and OCXO) and the closer I looked the less I was impressed. The one feature that was a show-stopper for me was that the TCXO version would not outperform the OCXO version even if you gave it a BVA or maser as external reference to the counter.

That means in order to get decent performance out of the 53230A you must buy the overpriced OCXO version of the counter. I wonder if anyone else has run into this? Maybe my eval units were out of spec. Or, I wonder if anyone has opened their 53230A and hacked the timebase PLL to overcome this problem?

Anyway, that led to me checking out a pile of 53132A counters to see how well they performed.

In these tests I like to use slightly drifting, ultrastable, independent inputs instead of the old "BNC tee" trick where CH1=CH2 or CH1=CH2=REF. What you want is to see is not only the RMS noise in a measurement, but also how consistent the TI measurements are across the entire fundamental period of the inputs or timebase.

For my test I used two ultrastable sources with 1e-12 or 1e-11 frequency offset. At 1e-11 you can scan an entire 100 ns period in 10,000 seconds (under 3 hours). I'd have to look at my notes to see what I did with the REF input. I think I tried REF=CH1 and REF=CH2 and REF=3rd independent source. But the main goal was to see the interaction between CH1 and CH2 because that's the mode used by any TI measurement.

Right, there's no paper that I could find yet. Instead I was planning on taking several models of popular high-end TI counters (SR620, HP5370, CNT-91, 53132A, 53230A) and run them all through the same offset/linearity test to investigate the "fine structure" of their measurement errors, as was done in the Leiby paper. If you have some measurement setup suggestions beyond what I already did with the 53132 counters, let me know.

Thanks,
/tvb

Tom,

On 02/28/2015 06:10 PM, Tom Van Baak wrote:

Yes, it makes good sense to follow up with those.

The paper is indeed a good find.

Indeed. The time error over the time-base period is relevant to measure,
but also you have cross-talk from time-base into channels as well as
cross-talk between channels. For the frequency case, you might not
expect there to be cross-talk, but there will be if the frequency
measure uses the start and stop channels.

Indeed. It can be hard to separate the non-linearity of a channel (over
the time-base period) from the cross-talk from reference to channel.
The non-linearity usually has a periodicity over the time-base reference
due to the use of a coarse counter frequency (such as 90, 100, 200 and
500 MHz) where as some (HP5335A, HP5334A/B) uses the time-base directly
as coarse counters.

Leiby's paper is focused on the frequency measurement and in particular
the non-linearities of the hardware in relation to frequency
measurements. The underlying model is time errors and considering that
the frequency estimate f = events/(t_stop - t_start) the non-linearities
in the time estimations t_stop and t_start will be subtracted from each
other. As the number of complete cycles of error increases with tau, the
remaining time error within such a period will be divided by a tau.
Consider the period formula
t_period = (t_stop - t_start)/events
Consider that events = tauf_1, t_start = 0 + te_start, t_stop = tau +
te_stop (approximation for understanding) we get
t_period = 1/f_1 + (te_stop - te_start)/(tauf_1)

No wonder that the period (and thus frequency) measure errors varies
with tau and measured frequency.

Rather than measuring with free-floating oscillators, I have been
considering using frequency syntesizers as in Leiby's article and
programmable delays. That way I can stay at a particular delay and bang
the same point and get statistics. The histogram will give me
information about the offset and coupling properties.

I think this could be an interesting paper maybe.

Cheers,
Magnus