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Re: [time-nuts] Broken Ovenaire OSC 85-50

BG
Bruce Griffiths
Sat, Jul 4, 2009 2:11 AM

Mike Monett wrote:

Mike Monett wrote:

A couple of things. First, trying to measure the currents  in the
circuit with  a ferrite toroid won't do you much good.  You don't
know what the currents should be, and the secondary of the toroid
transformer requires  a termination resistor.  The  value changes
with the turns ratio.

Just from  looking  at  the  circuit,  the  RF  currents  will be
extremely low.  This  requires  a large number  of  turns  on the
secondary, which  will  probably resonate at or  below  the 10MHz
operating frequency due to stray capacitance from  the connection
to the scope. So it is unlikely you will get any  useful progress
in this direction.

Uncalibrated speculation isnt helpful.

Estimates of  the actual current would be more  helpful  than mere
hand waving.

All the  discussion up till now has been handwaving. And  you forgot
the termination  resistor  that  is  required  on  the transformer
secondary. I  provide  means to get the true  voltages  and currents
later.

Tektronix current  probes  don't  seem  to  suffer  from such
limitations.

If the  current  is  very  low then a  low  noise  preamp  is also
necessary.

Obviously. But the currents are likely to be in the microamp region.

Not only  is  that  very hard to measure,  especially  at  10MHz, it
doesn't do any good if you don't know what they are supposed to be.

But why  bother  trying  to  measure the  current.  If  you  have an
accurate spice  model, you know the voltages in  the  circuit. These
can be  measured  much  easier and more  accurately  than  trying to
measure microamps in a 10MHz crystal tank.

However, from  the  values  on your  schematic,  the  output tank
circuit resonates  at  9.602MHz with a Q of 9.6. So  the  tank is
already well  below  resonance,  which  attenuates  the output
voltage.

Any stray  capacitance  you  add to the  circuit  will  bring the
resonant frequency lower, further aggravating the loss in signal.

The output tank is tapped with the 75pF and 91pF in  series. This
further attenuates the signal.

I'd change the circuit to a single capacitor across the tank with
a small trim capacitor to tune it to resonance.

This is usually a bad idea.

Unless the  circuit  components have  been  altered,  the designer
intended that the collector load be capacitive.

Using a  resonant  circuit  tuned  to  resonance  at  the crystal
frequency as a load inevitably degrades the amplifier  phase shift
tempco and the phase noise.

Without putting the circuit in spice, it seems he is  operating near
the -3dB point. The slope of the phase vs frequency is pretty linear
from the +/- 3dB points through resonance.

So it  doesn't  matter much where the tank is  tuned.  It  will give
about the same phase noise anywhere.

If and only if the tank operating point is within the region where the
phase slope is approximately linear.

Operating down  the  side of the resonance curve is  a  good  way to
convert AM noise into phase noise.

A good oscillator has very low AM noise.

A detuned  tank avoids the dc voltage drop and  the  flicker phase
noise associated with just using a collector resistor as a load.

I think  he really meant to tune the tank to resonance.  The problem
may simply be incorrect values shown for the tank components.

Perhaps the design is so old that the designer was unaware of the phase
noise implications of using a tuned tank.

The capacitively tapped circuit increases the current in the load.

For a low impedance load. But we don't know what the load is.

The load for the oscillator buffer is well defined,
The output stage load lies somewhere between 0 and 330 ohms.

A common  base amplifier could be used with some advantage  in the
output buffer but there are better circuits.

To get  the  signal  into 50 ohms  for  distribution,  I'd  add a
limiter if  you  can  tolerate a square wave  output,  or  a good
emitter follower  if you need a sine wave. Take  the  output from
the collector of the 2N2369 to get the maximum signal amplitude.

Emitter followers are not usually a good idea as they are somewhat
intolerant of short circuits (accidents do happen)  and capacitive
loading.

Short circuit protection is easy to add.

Yes but instability due to capacitive loading can only be cured by
careful design.
Using a series resistor in series with the output  can work but reduces
the signal level.

Capacitive loading  means  the tank would be  operating  further off
resonance, and the basic circuit diagram shows this is unlikely.

There are single transistor circuits with better reverse isolation
than an emitter follower.

Right now  there  is nothing on the output except the  tank.  So any
added isolation would be an improvement.

Its better to do the analysis and design an appropriate stage than just
chuck in an emitter follower.

Your original  post mentions an output amplitude of 20mV.  If the
normal amplitude  is around 2V, this represents a  loss  of 40dB.
This is  a huge loss in signal. The circuit  obviously  worked at
one time, so there may well be some other hidden problem.

It is possible the crystal is damaged, but this seems unlikely. A
crystal oscillator probably won't even start if the  signal level
is down 40dB.

You can check the oscillator and crystal in SPICE.  Normally, the
high Q of the crystal will make the analysis very slow.  It could
take many  hours  for  the simulation  to  begin  oscillating and
stabilize at the final amplitude. The transient analysis requires
a very  fine  time step for accuracy, and you  could  run  out of
memory before the simulation was complete.

Not so  (although some Spice variants may still  suffer  from this
problem) this may once have been true with a slow PC.

Depends on the time step. To get any accuracy, you need a  fine time
step. This is slow on any computer, and it eats a lot of memory.

It depends  on the actual oscillator circuit  some  circuits start
faster if  one  sets up a suitable initial  condition  such  as an
initial current in the inductor in the crystal  equivalent circuit
but you  have  to  get the  current  right.  With  some oscillator
circuits doing this can slow the simulated oscillator startup.

I have  developed  a  much  faster  way  of  analyzing  a crystal
oscillator in  SPICE.  Instead of requiring tens  or  hundreds of
thousands of simulated cycles, this method gives accurate results
in only  a  few dozen cycles. For  more  information,  please see
"SPICE Analysis of Crystal Oscillators"

This isn't new its been around for decades.

Please, Bruce,  show me one reference that uses my approach.  Do not
confuse previous  attempts that inject a starting  impulse  into the
tank to get the oscillation going.

My method initializes the tank to the exact point in the cycle where
the current through the crystal motional inductance is at maximum.

You can  calculate this current exactly, and set  the  oscillator to
whatever crystal dissipation you desire.

When the  transient analysis starts, the tank  proceeds  through the
cycle as  if it had been running forever. It does not  need hundreds
or thousands  of  cycles  to get  the  amplitude  stabilized.  It is
already stabilized,  and  the only thing you have to do  is  let the
electronics catch up.

This does not occur with previous methods of injecting a  pulse into
the tank. This still take many cycles to get the  oscillator running
and to stabilize the amplitude.

The next  trick  is  to  measure  the  amplitude  of  the  peaks to
parts-per-million accuracy  so  you  can  see  if  the  amplitude is
increasing or decreasing.

This relies on the peak search capability in Microcap SPICE. LTspice
and PSPICE  do  not  have the capability to  do  this,  and Microcap
didn't have  it in previous releases. So I am  pretty  confident you
have never seen this approach before.

Please provide references to support your claim.

You can estimate the value of the crystal ESR by finding the Q of
your crystal and working backwards.

Thanks,

Mike

~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
from your next post:

Blindly adding a wide bandwidth limiter will degrade the phase noise
if the input signal slew rate is too low.

In such  cases ts better to use a cascade of limiters  each  with an
output filter and a well defined gain at the zero crossing.

The output  filter and the gain (at zero crossing) of each  stage is
selected to minimse the jitter at the output.

Bruce

Bruce, you have mentioned this many times. I have a hard time seeing
how this could work.

Its almost trivial, you actually need to maximise the zero crossing
slope to noise ratio for each stage of the limiter.
Using a wide bandwidth limiter reduces the output noise to slope ratio
below that of a limiter with the optimum bandwidth.
A few Spice simulations or hand calculations with a fixed gain limiter
will quickly show that there is an optimum filter cutoff frequency that
produces the lowest output jitter.
The slope gain required to ensure that the jitter is well below that of
any subsequent logic is readily calculated.
If the signal slew rate is high enough the limiter design is relatively
non critical.
Its also necessary to optimise the gain distribution within the limiter.
Using a single high gain limiter is far from the optimum approach for
low slew rate signals.
For a given signal and slope gain there is also an optimum number of
limiter stages.
However even at 1Hz there isn't usually a great deal of improvement
beyond 6 limiter stages.
At low frequencies the performance of a single stage limiter can be
1,000,000 times worse than a 6 stage limiter.
At higher frequencies 1-3 stages may suffice, depending on the signal
slew rate and the jitter characteristics of the following circuitry.

Linear systems  do  not  care  where  the  filters  are  located. A
zero-crossing detector  (limiter)  is  linear  through  the zero
crossing.

A limiter isn't a linear system except near the zero crossing.

So all you really need is one limiter with sufficient gain,  and one
filter on  the output to cut the high frequency  noise  generated at
the input stage of the limiter.

It has been obvious (for example it has long been known and shown in
practice that the performance using such a system is inferior to a
system using a set of cascaded limiters with each successive  stage
having a greater gain and bandwidth than the previous stage however
despite several attempts the optimum gain and bandwidth distribution
remained unknown) for decades before the Collins paper that this isn't
true in general. If one only needs a modest slope gain then a low gain
single stage limiter with an appropriate output filter may suffice.

However, none of this helps with the flicker noise generated  at the
input of the limiter.

What mechanism do you have in mind?
If you are naive enough to use a limiter stage without (series) feedback
to linearise its performance near zero crossing then flicker noise may
be an issue.
If the limiter stage has too high a dc and low frequency gain then
flicker noise can also be a problem.
With sufficient feedback and not too high a dc gain the limiter flicker
phase noise can easily be made much lower than that of a crystal oscillator.

This probably  contains most of the noise power, so  it  is doubtful
that any arrangement of low-pass filters will do much good.

Only if you limit yourself to using a limiter without signal frequency
feedback in the active region.
A limiter stage generates very little noise when its output is actually
at one of the limits.

Can you  post  a spice analysis of your approach to show  us  how it
works?

Oliver Collins did the fundamental analysis in the mid 90's:
"The Design of Low Jitter Hard Limiters" IEEE transactions on
Communications, Vol 44 No 5, May 1996 pp 601-608 (no it isn't free, you
either have to pay to download it, or find a library that gets this Journal)
His analysis (possibly with suitable extensions to take into account the
fact that device noise tends to increase at high frequencies) also
applies to RF limiters.

Its almost trivial to extend Collins' analysis to the case where the
noise of each limiter stage isn't the same as the other limiter stages.
A Spice analysis isn't particularly helpful.
Whilst one can use it to estimate the output noise and output slope for
each limiter stage, simulating the resultant jitter is usually a little
problematic.

And don't forget the reference on the SPICE analysis of crystal osc.

Spice is merely a tool for numeral solution of a set of nonlinear
differential equations, the approach you use (and those that others use)
has been obvious for some 400 years.

Regards,

Mike

Bruce

Mike Monett wrote: > > Mike Monett wrote: > > >> A couple of things. First, trying to measure the currents in the > >> circuit with a ferrite toroid won't do you much good. You don't > >> know what the currents should be, and the secondary of the toroid > >> transformer requires a termination resistor. The value changes > >> with the turns ratio. > > >> Just from looking at the circuit, the RF currents will be > >> extremely low. This requires a large number of turns on the > >> secondary, which will probably resonate at or below the 10MHz > >> operating frequency due to stray capacitance from the connection > >> to the scope. So it is unlikely you will get any useful progress > >> in this direction. > > > Uncalibrated speculation isnt helpful. > > > Estimates of the actual current would be more helpful than mere > > hand waving. > > All the discussion up till now has been handwaving. And you forgot > the termination resistor that is required on the transformer > secondary. I provide means to get the true voltages and currents > later. > > > Tektronix current probes don't seem to suffer from such > > limitations. > > > If the current is very low then a low noise preamp is also > > necessary. > > Obviously. But the currents are likely to be in the microamp region. > > Not only is that very hard to measure, especially at 10MHz, it > doesn't do any good if you don't know what they are supposed to be. > > But why bother trying to measure the current. If you have an > accurate spice model, you know the voltages in the circuit. These > can be measured much easier and more accurately than trying to > measure microamps in a 10MHz crystal tank. > > >> However, from the values on your schematic, the output tank > >> circuit resonates at 9.602MHz with a Q of 9.6. So the tank is > >> already well below resonance, which attenuates the output > >> voltage. > > >> Any stray capacitance you add to the circuit will bring the > >> resonant frequency lower, further aggravating the loss in signal. > > >> The output tank is tapped with the 75pF and 91pF in series. This > >> further attenuates the signal. > > >> I'd change the circuit to a single capacitor across the tank with > >> a small trim capacitor to tune it to resonance. > > > This is usually a bad idea. > > > Unless the circuit components have been altered, the designer > > intended that the collector load be capacitive. > > > Using a resonant circuit tuned to resonance at the crystal > > frequency as a load inevitably degrades the amplifier phase shift > > tempco and the phase noise. > > Without putting the circuit in spice, it seems he is operating near > the -3dB point. The slope of the phase vs frequency is pretty linear > from the +/- 3dB points through resonance. > > So it doesn't matter much where the tank is tuned. It will give > about the same phase noise anywhere. > > If and only if the tank operating point is within the region where the phase slope is approximately linear. > Operating down the side of the resonance curve is a good way to > convert AM noise into phase noise. > > A good oscillator has very low AM noise. > > A detuned tank avoids the dc voltage drop and the flicker phase > > noise associated with just using a collector resistor as a load. > > I think he really meant to tune the tank to resonance. The problem > may simply be incorrect values shown for the tank components. > > Perhaps the design is so old that the designer was unaware of the phase noise implications of using a tuned tank. > > The capacitively tapped circuit increases the current in the load. > > For a low impedance load. But we don't know what the load is. > The load for the oscillator buffer is well defined, The output stage load lies somewhere between 0 and 330 ohms. > > A common base amplifier could be used with some advantage in the > > output buffer but there are better circuits. > > >> To get the signal into 50 ohms for distribution, I'd add a > >> limiter if you can tolerate a square wave output, or a good > >> emitter follower if you need a sine wave. Take the output from > >> the collector of the 2N2369 to get the maximum signal amplitude. > > > Emitter followers are not usually a good idea as they are somewhat > > intolerant of short circuits (accidents do happen) and capacitive > > loading. > > Short circuit protection is easy to add. > Yes but instability due to capacitive loading can only be cured by careful design. Using a series resistor in series with the output can work but reduces the signal level. > Capacitive loading means the tank would be operating further off > resonance, and the basic circuit diagram shows this is unlikely. > > > There are single transistor circuits with better reverse isolation > > than an emitter follower. > > Right now there is nothing on the output except the tank. So any > added isolation would be an improvement. > Its better to do the analysis and design an appropriate stage than just chuck in an emitter follower. > >> Your original post mentions an output amplitude of 20mV. If the > >> normal amplitude is around 2V, this represents a loss of 40dB. > >> This is a huge loss in signal. The circuit obviously worked at > >> one time, so there may well be some other hidden problem. > > >> It is possible the crystal is damaged, but this seems unlikely. A > >> crystal oscillator probably won't even start if the signal level > >> is down 40dB. > > >> You can check the oscillator and crystal in SPICE. Normally, the > >> high Q of the crystal will make the analysis very slow. It could > >> take many hours for the simulation to begin oscillating and > >> stabilize at the final amplitude. The transient analysis requires > >> a very fine time step for accuracy, and you could run out of > >> memory before the simulation was complete. > > > Not so (although some Spice variants may still suffer from this > > problem) this may once have been true with a slow PC. > > Depends on the time step. To get any accuracy, you need a fine time > step. This is slow on any computer, and it eats a lot of memory. > > > It depends on the actual oscillator circuit some circuits start > > faster if one sets up a suitable initial condition such as an > > initial current in the inductor in the crystal equivalent circuit > > but you have to get the current right. With some oscillator > > circuits doing this can slow the simulated oscillator startup. > > >> I have developed a much faster way of analyzing a crystal > >> oscillator in SPICE. Instead of requiring tens or hundreds of > >> thousands of simulated cycles, this method gives accurate results > >> in only a few dozen cycles. For more information, please see > >> "SPICE Analysis of Crystal Oscillators" > > > This isn't new its been around for decades. > > Please, Bruce, show me one reference that uses my approach. Do not > confuse previous attempts that inject a starting impulse into the > tank to get the oscillation going. > > > My method initializes the tank to the exact point in the cycle where > the current through the crystal motional inductance is at maximum. > > You can calculate this current exactly, and set the oscillator to > whatever crystal dissipation you desire. > > When the transient analysis starts, the tank proceeds through the > cycle as if it had been running forever. It does not need hundreds > or thousands of cycles to get the amplitude stabilized. It is > already stabilized, and the only thing you have to do is let the > electronics catch up. > > This does not occur with previous methods of injecting a pulse into > the tank. This still take many cycles to get the oscillator running > and to stabilize the amplitude. > > The next trick is to measure the amplitude of the peaks to > parts-per-million accuracy so you can see if the amplitude is > increasing or decreasing. > > This relies on the peak search capability in Microcap SPICE. LTspice > and PSPICE do not have the capability to do this, and Microcap > didn't have it in previous releases. So I am pretty confident you > have never seen this approach before. > > Please provide references to support your claim. > > >> http://pstca.com/spice/xtal/clapp.htm > > >> You can estimate the value of the crystal ESR by finding the Q of > >> your crystal and working backwards. > > >> Thanks, > > >> Mike > ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ > from your next post: > > > Blindly adding a wide bandwidth limiter will degrade the phase noise > > if the input signal slew rate is too low. > > > In such cases ts better to use a cascade of limiters each with an > > output filter and a well defined gain at the zero crossing. > > > The output filter and the gain (at zero crossing) of each stage is > > selected to minimse the jitter at the output. > > > Bruce > > Bruce, you have mentioned this many times. I have a hard time seeing > how this could work. > Its almost trivial, you actually need to maximise the zero crossing slope to noise ratio for each stage of the limiter. Using a wide bandwidth limiter reduces the output noise to slope ratio below that of a limiter with the optimum bandwidth. A few Spice simulations or hand calculations with a fixed gain limiter will quickly show that there is an optimum filter cutoff frequency that produces the lowest output jitter. The slope gain required to ensure that the jitter is well below that of any subsequent logic is readily calculated. If the signal slew rate is high enough the limiter design is relatively non critical. Its also necessary to optimise the gain distribution within the limiter. Using a single high gain limiter is far from the optimum approach for low slew rate signals. For a given signal and slope gain there is also an optimum number of limiter stages. However even at 1Hz there isn't usually a great deal of improvement beyond 6 limiter stages. At low frequencies the performance of a single stage limiter can be 1,000,000 times worse than a 6 stage limiter. At higher frequencies 1-3 stages may suffice, depending on the signal slew rate and the jitter characteristics of the following circuitry. > Linear systems do not care where the filters are located. A > zero-crossing detector (limiter) is linear through the zero > crossing. > > A limiter isn't a linear system except near the zero crossing. > So all you really need is one limiter with sufficient gain, and one > filter on the output to cut the high frequency noise generated at > the input stage of the limiter. > > It has been obvious (for example it has long been known and shown in practice that the performance using such a system is inferior to a system using a set of cascaded limiters with each successive stage having a greater gain and bandwidth than the previous stage however despite several attempts the optimum gain and bandwidth distribution remained unknown) for decades before the Collins paper that this isn't true in general. If one only needs a modest slope gain then a low gain single stage limiter with an appropriate output filter may suffice. > However, none of this helps with the flicker noise generated at the > input of the limiter. > > What mechanism do you have in mind? If you are naive enough to use a limiter stage without (series) feedback to linearise its performance near zero crossing then flicker noise may be an issue. If the limiter stage has too high a dc and low frequency gain then flicker noise can also be a problem. With sufficient feedback and not too high a dc gain the limiter flicker phase noise can easily be made much lower than that of a crystal oscillator. > This probably contains most of the noise power, so it is doubtful > that any arrangement of low-pass filters will do much good. > > Only if you limit yourself to using a limiter without signal frequency feedback in the active region. A limiter stage generates very little noise when its output is actually at one of the limits. > Can you post a spice analysis of your approach to show us how it > works? > > Oliver Collins did the fundamental analysis in the mid 90's: "The Design of Low Jitter Hard Limiters" IEEE transactions on Communications, Vol 44 No 5, May 1996 pp 601-608 (no it isn't free, you either have to pay to download it, or find a library that gets this Journal) His analysis (possibly with suitable extensions to take into account the fact that device noise tends to increase at high frequencies) also applies to RF limiters. Its almost trivial to extend Collins' analysis to the case where the noise of each limiter stage isn't the same as the other limiter stages. A Spice analysis isn't particularly helpful. Whilst one can use it to estimate the output noise and output slope for each limiter stage, simulating the resultant jitter is usually a little problematic. > And don't forget the reference on the SPICE analysis of crystal osc. > Spice is merely a tool for numeral solution of a set of nonlinear differential equations, the approach you use (and those that others use) has been obvious for some 400 years. > Regards, > > Mike > > Bruce