Empathy List Archives

AB

abdulhai_basha@nrsc.gov.in

Thu, May 29, 2025 8:44 AM

Hi.
I am working on IRIG signal generation using FPGA. It requires sub second time information such as tenth's of a second and hundredth's of a second.
I have a 10MHz signal in sync with1PPS. How to generate sub second time information and extend to µs range.

Thanks & Regards
Abdul

Hi. I am working on IRIG signal generation using FPGA. It requires sub second time information such as tenth's of a second and hundredth's of a second. I have a 10MHz signal in sync with1PPS. How to generate sub second time information and extend to µs range. Thanks & Regards Abdul

BC

Bob Camp

Fri, May 30, 2025 12:53 PM

Hi

If your 10 MHz is in sync with your PPS then the 10 MHz is giving you “ticks” every 100 ns. That should be plenty good enough to generate whatever IRIG you need. How you put in the divider and sync it to the PPS is highly dependent on the design software you are using. The normal “clock boundary” circuits should be applied going from the PPS to the 10 MHz side of things.

Bob

On May 29, 2025, at 4:44 AM, ABDUL HAI via time-nuts time-nuts@lists.febo.com wrote:

Hi.
I am working on IRIG signal generation using FPGA. It requires sub second time information such as tenth's of a second and hundredth's of a second.
I have a 10MHz signal in sync with1PPS. How to generate sub second time information and extend to µs range.

Thanks & Regards
Abdul

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To unsubscribe send an email to time-nuts-leave@lists.febo.com

Hi If your 10 MHz is in sync with your PPS then the 10 MHz is giving you “ticks” every 100 ns. That should be plenty good enough to generate whatever IRIG you need. How you put in the divider and sync it to the PPS is highly dependent on the design software you are using. The normal “clock boundary” circuits should be applied going from the PPS to the 10 MHz side of things. Bob > On May 29, 2025, at 4:44 AM, ABDUL HAI via time-nuts <time-nuts@lists.febo.com> wrote: > > Hi. > I am working on IRIG signal generation using FPGA. It requires sub second time information such as tenth's of a second and hundredth's of a second. > I have a 10MHz signal in sync with1PPS. How to generate sub second time information and extend to µs range. > > > > Thanks & Regards > Abdul > _______________________________________________ > time-nuts mailing list -- time-nuts@lists.febo.com > To unsubscribe send an email to time-nuts-leave@lists.febo.com

JL

Jim Lux

Wed, Jun 11, 2025 3:54 PM

I'm pretty sure there's some FPGA source code out there to do the IRIG stuff, once you have the clock.
here's one for a NI FPGA
https://forums.ni.com/t5/Example-Code/IRIG-B-Implementation-in-LabVIEW-FPGA/ta-p/3996148
Open Cores has one in VHDL
https://opencores.org/websvn/filedetails?repname=irig_regenerator&path=%2Firig_regenerator%2Ftrunk%2Frtl%2Firig_time_pack.vhd&rev=0

It takes a 1pps input and a "sys_clk". There's a clock synthesizer that makes a 1 MHz clock which runs the whole core.
It also has a nice schematic (in ASCII) of what you need to generate a IRIG compatible signal with the right voltages, and such.

The rest is left as an exercise for the reader. Abdul, your work might already be mostly done!

On Fri, 30 May 2025 08:53:05 -0400, Bob Camp via time-nuts time-nuts@lists.febo.com wrote:

Hi

If your 10 MHz is in sync with your PPS then the 10 MHz is giving you “ticks” every 100 ns. That should be plenty good enough to generate whatever IRIG you need. How you put in the divider and sync it to the PPS is highly dependent on the design software you are using. The normal “clock boundary” circuits should be applied going from the PPS to the 10 MHz side of things.

Bob

On May 29, 2025, at 4:44 AM, ABDUL HAI via time-nuts wrote:

Hi.
I am working on IRIG signal generation using FPGA. It requires sub second time information such as tenth's of a second and hundredth's of a second.
I have a 10MHz signal in sync with1PPS. How to generate sub second time information and extend to µs range.

Thanks & Regards
Abdul

time-nuts mailing list -- time-nuts@lists.febo.com
To unsubscribe send an email to time-nuts-leave@lists.febo.com

I'm pretty sure there's some FPGA source code out there to do the IRIG stuff, once you have the clock. here's one for a NI FPGA https://forums.ni.com/t5/Example-Code/IRIG-B-Implementation-in-LabVIEW-FPGA/ta-p/3996148 Open Cores has one in VHDL https://opencores.org/websvn/filedetails?repname=irig_regenerator&path=%2Firig_regenerator%2Ftrunk%2Frtl%2Firig_time_pack.vhd&rev=0 It takes a 1pps input and a "sys_clk". There's a clock synthesizer that makes a 1 MHz clock which runs the whole core. It also has a nice schematic (in ASCII) of what you need to generate a IRIG compatible signal with the right voltages, and such. The rest is left as an exercise for the reader. Abdul, your work might already be mostly done! On Fri, 30 May 2025 08:53:05 -0400, Bob Camp via time-nuts <time-nuts@lists.febo.com> wrote: Hi If your 10 MHz is in sync with your PPS then the 10 MHz is giving you “ticks” every 100 ns. That should be plenty good enough to generate whatever IRIG you need. How you put in the divider and sync it to the PPS is highly dependent on the design software you are using. The normal “clock boundary” circuits should be applied going from the PPS to the 10 MHz side of things. Bob > On May 29, 2025, at 4:44 AM, ABDUL HAI via time-nuts wrote: > > Hi. > I am working on IRIG signal generation using FPGA. It requires sub second time information such as tenth's of a second and hundredth's of a second. > I have a 10MHz signal in sync with1PPS. How to generate sub second time information and extend to µs range. > > > > Thanks & Regards > Abdul > _______________________________________________ > time-nuts mailing list -- time-nuts@lists.febo.com > To unsubscribe send an email to time-nuts-leave@lists.febo.com _______________________________________________ time-nuts mailing list -- time-nuts@lists.febo.com To unsubscribe send an email to time-nuts-leave@lists.febo.com

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Generating Sub-second from 10MHZ clock.