Hello, I need to establish direct routing between the USRP X410's front panel GPIO pins and custom RFNoC blocks. Specifically, I want to read the GPIO signals directly into my RFNoC block. Does anyone have experience implementing such direct GPIO-to-RFNoC connection on the X410? Any examples or technical documentation would be helpful.   Thanks

Hi, this is currently not possible without changing the UHD core manually and re-routing those GPIO lines in the Verilog core code. Some years ago I opened a feature request, it contains some hints on what others tried and what would be required. Unfortunately, I never got an answer. Would be wonderful if you could support that by voting on the issue and express your interest there. Or if you manage to get it working, share your solution with a PR. Here is the link: https://github.com/EttusResearch/uhd/issues/666 Best regards Philipp Am 3.2.25 um 9:00 schrieb meni.dali@sabra-microsystems.com: > > Hello, > > I need to establish direct routing between the USRP X410's front panel > GPIO pins and custom RFNoC blocks. > > Specifically, I want to read the GPIO signals directly into my RFNoC > block. > > Does anyone have experience implementing such direct GPIO-to-RFNoC > connection on the X410? > > Any examples or technical documentation would be helpful. > > Thanks > > > _______________________________________________ > USRP-users mailing list -- usrp-users@lists.ettus.com > To unsubscribe send an email to usrp-users-leave@lists.ettus.com

I'm working on the same thing, so yes this would be super useful. Does Ettus Research have any update on that GitHub issue #666? Here's the link again: https://github.com/EttusResearch/uhd/issues/666 Sincerely, Alex-M-Humberstone PhD Student Klipsch School of Electrical Engineering New Mexico State University (NMSU) Las Cruces, New Mexico, 88003 alex.m.humberstone@gmail.com https://ece.nmsu.edu/ On Mon, 3 Feb 2025 at 02:15, Philipp Niedermayer <p.niedermayer@gsi.de> wrote: > Hi, > > this is currently not possible without changing the UHD core manually > and re-routing those GPIO lines in the Verilog core code. Some years ago > I opened a feature request, it contains some hints on what others tried > and what would be required. Unfortunately, I never got an answer. > > Would be wonderful if you could support that by voting on the issue and > express your interest there. Or if you manage to get it working, share > your solution with a PR. > > Here is the link: https://github.com/EttusResearch/uhd/issues/666 > > Best regards > Philipp > > > Am 3.2.25 um 9:00 schrieb meni.dali@sabra-microsystems.com: > > > > Hello, > > > > I need to establish direct routing between the USRP X410's front panel > > GPIO pins and custom RFNoC blocks. > > > > Specifically, I want to read the GPIO signals directly into my RFNoC > > block. > > > > Does anyone have experience implementing such direct GPIO-to-RFNoC > > connection on the X410? > > > > Any examples or technical documentation would be helpful. > > > > Thanks > > > > > > _______________________________________________ > > USRP-users mailing list -- usrp-users@lists.ettus.com > > To unsubscribe send an email to usrp-users-leave@lists.ettus.com > _______________________________________________ > USRP-users mailing list -- usrp-users@lists.ettus.com > To unsubscribe send an email to usrp-users-leave@lists.ettus.com >

Hi Alex, I know that Ettus Research is aware of this and it's being looked at as a possible feature. In the current version of UHD, you still have to make manual changes to the FPGA to access the GPIO from RFNoC. The changes aren't particularly difficult, but it can be intimidating if you're not familiar with FPGA code or RFnoC. It basically involves following the DIOA_FPGA and/or DIOB_FPGA signals through the design and disconnecting them cleanly from the normal logic, and then reconnecting them to the RFNoC image. Thanks, Wade On Thu, Feb 6, 2025 at 7:39 AM Alex Humberstone < alex.m.humberstone@gmail.com> wrote: > I'm working on the same thing, so yes this would be super useful. > > Does Ettus Research have any update on that GitHub issue #666? > > Here's the link again: > https://github.com/EttusResearch/uhd/issues/666 > > > Sincerely, > Alex-M-Humberstone > PhD Student > Klipsch School of Electrical Engineering > New Mexico State University (NMSU) > Las Cruces, New Mexico, 88003 > alex.m.humberstone@gmail.com > https://ece.nmsu.edu/ > > > > On Mon, 3 Feb 2025 at 02:15, Philipp Niedermayer <p.niedermayer@gsi.de> > wrote: > >> Hi, >> >> this is currently not possible without changing the UHD core manually >> and re-routing those GPIO lines in the Verilog core code. Some years ago >> I opened a feature request, it contains some hints on what others tried >> and what would be required. Unfortunately, I never got an answer. >> >> Would be wonderful if you could support that by voting on the issue and >> express your interest there. Or if you manage to get it working, share >> your solution with a PR. >> >> Here is the link: https://github.com/EttusResearch/uhd/issues/666 >> >> Best regards >> Philipp >> >> >> Am 3.2.25 um 9:00 schrieb meni.dali@sabra-microsystems.com: >> > >> > Hello, >> > >> > I need to establish direct routing between the USRP X410's front panel >> > GPIO pins and custom RFNoC blocks. >> > >> > Specifically, I want to read the GPIO signals directly into my RFNoC >> > block. >> > >> > Does anyone have experience implementing such direct GPIO-to-RFNoC >> > connection on the X410? >> > >> > Any examples or technical documentation would be helpful. >> > >> > Thanks >> > >> > >> > _______________________________________________ >> > USRP-users mailing list -- usrp-users@lists.ettus.com >> > To unsubscribe send an email to usrp-users-leave@lists.ettus.com >> _______________________________________________ >> USRP-users mailing list -- usrp-users@lists.ettus.com >> To unsubscribe send an email to usrp-users-leave@lists.ettus.com >> > _______________________________________________ > USRP-users mailing list -- usrp-users@lists.ettus.com > To unsubscribe send an email to usrp-users-leave@lists.ettus.com >

Hello, I didn’t make RFNoC block - just some custom module that was connected to ‘gpio_out_fabric_a’ of ‘x4xx_core_common_i’ in ‘x4xx_core.v‘: https://github.com/ptrkrysik/uhd/commit/a6275494b173187b11205fe33b1fc937d477e9b5 That logic took LSB from imaginary part of sample and sent it to a GPIO line (which had to be set to **USER_APP** mode - https://files.ettus.com/manual/page_x400_gpio_api.html). I’ve been looking how to do that from RFNoC and it looked that I would have to manually edit automatically generated verilog files to connect the GPIO there (not very entertaining when you have to do that on each change of the yaml flowgraph). However, the documentation seemed to suggest also possibility of connecting verilog’s wires in the yaml files. I would imagine that this would work this way: create some input for RFNoC block with unique name and connect it to some wire that would be connected to i.e. ‘user_app_in_a’. After that in the generated verilog those would be connected together. That would be much better solution. But I never tried it. Does anyone have experience with this? Or was I wrong getting impression it might be possible? Best Regards,\ Piotr Krysik