Questions about TAC frontend, and some measurements
Hello, hope you all had a happy Christmas.
Back to the topic.
Bob Camp asked:
Hi
One very simple question - how good would it do if you just did it all
with logic gates? Tri-state buffers and things like that….
Now that you are up to a 100 to 200 ns long pulse, a lot of the fiddly
stuff about "can't get a 2 ns pulse through it" goes away.
I'm not suggesting you tear up what you have. It's just something else
to try and compare
Bob
Bob, are you hinting to something like the last mail from Bruce?
I.e. to use a tristate buffer to charge the capacitor?
If not can you explicit what are you thinking? :)
Thanks also to Alan Melia and Tom Miller for the details about
bjt saturation .
Bruce, about the tempco of the current generators,
There is the led in series with a BE junction.
The blue leds should have a tempco in mV per °C similar
to th BE junction, dont know the red ones.
Would it be better to use something like a 4.7 or 5.1V
zener? If I remember correctly these zener voltage
shuld cancel most of the BE tempco.
And what about a TL431 instead of the led+bjt?
The Avago diodes are pretty costly :)
Is that circuit working like the internals of ECL logic
families?
The simplest (lowest part count and least number of power supplies)
consists of a tristate buffer driving an RC circuit.
The PPS signal is connected directly to the buffer input whilst the
output of the PPS synchroniser (at least 2 stages to minimise the
probability of metastabilty at the synchroniser output) drives the
buffer tristate control input.
A 2 stage syncronizer is composed of 3 FF?
I.e. clock in parallel to 3 FF, PPS to the
first D, Q from the first to D of the second,
same from the second to the thid, and Q from
the third to out. Let's assume that the inputs
from PPS and 10MHz are fast enough, what can still
generate metastability? Setup time violation?
The RC network starts charging when the PPS signal goes high and
stops when the synchroniser output goes high.
The capacitor charging is nonlinear but this is easily corrected in
software.
The capacitor is connected between the input of a capacitive charge
redistribution ADC and ground.
Software correction for the effect of charging the charge ADC input
capacitance is also required.
I see you are stressing the fact of using a capacitive charge
redistribution adc. I dont know much about the internals
of the ADC devices, can you suggest a partnumber for an example?
Suitable fast single gate tristate drives are readily available.
With low tempco resistors and capacitors the TAC gain tempco can be
200pmm/C or less.
The only disadvantages are the increased software complexity and the
need for an extra bit of ADC resolution to maintain TAC resolution.
The 3-state buffer + R-C seem an elegant solution for a microcontroller
based thing, I'v given an eye to logic buffers, and seem that all
suggest that the Hi-Z state leackage current is not very well
specified, but something around 1uA, that means that cap's voltage
after
the pulse can rapidly (and unpredictabily?)change due to leackage.
I imagine also that the leackage of the buffer will vary with
temperature.
The ADC of the micro is pretty fast, I shuld check the datasheet
but I remember around 1uS per conversion, what would happen connecting
directly the micro ADC to the charged cap? And sync the ADC to sample
immediately (few uS) after the pulse. Could the loading from the
s/h capacitance be corrected in fw?
Bruce
By the way, I updated my miserable schematic, I tried a simple
mod to avoid the saturation of the switches. Only because I had
it already built: http://pastebin.com/9VHkhmSv
Now I'm chasing the origin of the drift variation, logging
the temperatures and voltages. More on this as soon as I
have some data.
Thank you all,
Fabio.
Hi
You should check out the leakage of a typical tristate buffer. It's specified at a level that makes it easy to test. Most of the parts you find have very low leakage. Varicap diodes are similar in that respect, the leakage of real parts is much lower than the 1 ua you see on the old specs.
The likely qualifier on all that is "at room temperature". I'm sure the leakage goes a bit nuts as the parts get to 125C.
Bob
On Dec 26, 2012, at 5:26 AM, Fabio Eboli fabioeb@quipo.it wrote:
Hello, hope you all had a happy Christmas.
Back to the topic.
Bob Camp asked:
Hi
One very simple question - how good would it do if you just did it all with logic gates? Tri-state buffers and things like that….
Now that you are up to a 100 to 200 ns long pulse, a lot of the fiddly stuff about "can't get a 2 ns pulse through it" goes away.
I'm not suggesting you tear up what you have. It's just something else to try and compare
Bob
Bob, are you hinting to something like the last mail from Bruce?
I.e. to use a tristate buffer to charge the capacitor?
If not can you explicit what are you thinking? :)
Thanks also to Alan Melia and Tom Miller for the details about
bjt saturation .
Bruce, about the tempco of the current generators,
There is the led in series with a BE junction.
The blue leds should have a tempco in mV per °C similar
to th BE junction, dont know the red ones.
Would it be better to use something like a 4.7 or 5.1V
zener? If I remember correctly these zener voltage
shuld cancel most of the BE tempco.
And what about a TL431 instead of the led+bjt?
The Avago diodes are pretty costly :)
Is that circuit working like the internals of ECL logic
families?
The simplest (lowest part count and least number of power supplies)
consists of a tristate buffer driving an RC circuit.
The PPS signal is connected directly to the buffer input whilst the
output of the PPS synchroniser (at least 2 stages to minimise the
probability of metastabilty at the synchroniser output) drives the
buffer tristate control input.
A 2 stage syncronizer is composed of 3 FF?
I.e. clock in parallel to 3 FF, PPS to the
first D, Q from the first to D of the second,
same from the second to the thid, and Q from
the third to out. Let's assume that the inputs
from PPS and 10MHz are fast enough, what can still
generate metastability? Setup time violation?
The RC network starts charging when the PPS signal goes high and
stops when the synchroniser output goes high.
The capacitor charging is nonlinear but this is easily corrected in software.
The capacitor is connected between the input of a capacitive charge
redistribution ADC and ground.
Software correction for the effect of charging the charge ADC input
capacitance is also required.
I see you are stressing the fact of using a capacitive charge
redistribution adc. I dont know much about the internals
of the ADC devices, can you suggest a partnumber for an example?
Suitable fast single gate tristate drives are readily available.
With low tempco resistors and capacitors the TAC gain tempco can be
200pmm/C or less.
The only disadvantages are the increased software complexity and the
need for an extra bit of ADC resolution to maintain TAC resolution.
The 3-state buffer + R-C seem an elegant solution for a microcontroller
based thing, I'v given an eye to logic buffers, and seem that all
suggest that the Hi-Z state leackage current is not very well
specified, but something around 1uA, that means that cap's voltage after
the pulse can rapidly (and unpredictabily?)change due to leackage.
I imagine also that the leackage of the buffer will vary with temperature.
The ADC of the micro is pretty fast, I shuld check the datasheet
but I remember around 1uS per conversion, what would happen connecting
directly the micro ADC to the charged cap? And sync the ADC to sample
immediately (few uS) after the pulse. Could the loading from the
s/h capacitance be corrected in fw?
Bruce
By the way, I updated my miserable schematic, I tried a simple
mod to avoid the saturation of the switches. Only because I had
it already built: http://pastebin.com/9VHkhmSv
Now I'm chasing the origin of the drift variation, logging
the temperatures and voltages. More on this as soon as I
have some data.
Thank you all,
Fabio.
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Fabio Eboli wrote:
Hello, hope you all had a happy Christmas.
Back to the topic.
Bob Camp asked:
Hi
One very simple question - how good would it do if you just did it
all with logic gates? Tri-state buffers and things like that….
Now that you are up to a 100 to 200 ns long pulse, a lot of the
fiddly stuff about "can't get a 2 ns pulse through it" goes away.
I'm not suggesting you tear up what you have. It's just something
else to try and compare
Bob
Bob, are you hinting to something like the last mail from Bruce?
I.e. to use a tristate buffer to charge the capacitor?
If not can you explicit what are you thinking? :)
Thanks also to Alan Melia and Tom Miller for the details about
bjt saturation .
Bruce, about the tempco of the current generators,
There is the led in series with a BE junction.
The blue leds should have a tempco in mV per °C similar
to th BE junction, dont know the red ones.
Similar.
Would it be better to use something like a 4.7 or 5.1V
zener? If I remember correctly these zener voltage
shuld cancel most of the BE tempco.
And what about a TL431 instead of the led+bjt?
The BJT is essential to ensure that the current source has a high output
impedance.
Opamps dont help as most have insufficient gain at high frequencies.
The input capacitance of an opamp input connected directly to the
current source emitter isnt conducive to a high output impedance either.
Its better to drive the emitter of the second transistor with an npn
emitter follower thats part of a servo loop using a suitably decoupled
opamp (series resistor from the current source emitter to the inverting
input of the opamp) to set the emitter current of the current source
transistor.
The Avago diodes are pretty costly :)
Is that circuit working like the internals of ECL logic
families?
Yes apart from the lack of emitter follower outputs.
Its called current mode logic.
The simplest (lowest part count and least number of power supplies)
consists of a tristate buffer driving an RC circuit.
The PPS signal is connected directly to the buffer input whilst the
output of the PPS synchroniser (at least 2 stages to minimise the
probability of metastabilty at the synchroniser output) drives the
buffer tristate control input.
A 2 stage syncronizer is composed of 3 FF?
No 2 FF, the first FF is just a convenient means of stretching narrow
pulses and ensuring that the synchroniser input pulse width has the
required duration.
I.e. clock in parallel to 3 FF, PPS to the
first D, Q from the first to D of the second,
same from the second to the thid, and Q from
the third to out. Let's assume that the inputs
from PPS and 10MHz are fast enough, what can still
generate metastability? Setup time violation?
The RC network starts charging when the PPS signal goes high and
stops when the synchroniser output goes high.
The capacitor charging is nonlinear but this is easily corrected in
software.
The capacitor is connected between the input of a capacitive charge
redistribution ADC and ground.
Software correction for the effect of charging the charge ADC input
capacitance is also required.
I see you are stressing the fact of using a capacitive charge
redistribution adc. I dont know much about the internals
of the ADC devices, can you suggest a partnumber for an example?
Almost any modern SAR ADC such as the LTC1282 and later.
Suitable fast single gate tristate drives are readily available.
With low tempco resistors and capacitors the TAC gain tempco can be
200pmm/C or less.
The only disadvantages are the increased software complexity and the
need for an extra bit of ADC resolution to maintain TAC resolution.
The 3-state buffer + R-C seem an elegant solution for a microcontroller
based thing, I'v given an eye to logic buffers, and seem that all
suggest that the Hi-Z state leackage current is not very well
specified, but something around 1uA, that means that cap's voltage after
the pulse can rapidly (and unpredictabily?)change due to leackage.
I imagine also that the leackage of the buffer will vary with
temperature.
Kasper Pedersen has used this technique. http://n1.taur.dk/gpsdo2a.pdf
However he only used a single stage synchroniser which is far from ideal.
The ADC of the micro is pretty fast, I shuld check the datasheet
but I remember around 1uS per conversion, what would happen connecting
directly the micro ADC to the charged cap? And sync the ADC to sample
immediately (few uS) after the pulse. Could the loading from the
s/h capacitance be corrected in fw?
The best way is to have the ADC in sample mode whilst the capacitor is
being charged.
Wait sufficient time at the end of the charging process for the ADC
sampler to settle and then trigger a conversion.
If possible, its best for this conversion trigger to be generated by the
synchroniser (use a shift register 1st 2 stages for the synchroniser
prper and the following stages used to generate the required delay.
The effect of the sampling capacitance can be corrected in software to a
first approximation it merely changes the TAC gain.
Bruce
By the way, I updated my miserable schematic, I tried a simple
mod to avoid the saturation of the switches. Only because I had
it already built: http://pastebin.com/9VHkhmSv
Now I'm chasing the origin of the drift variation, logging
the temperatures and voltages. More on this as soon as I
have some data.
Thank you all,
Fabio.
Bruce
On Sun, 23 Dec 2012 22:45:40 +0100
Fabio Eboli FabioEb@quipo.it wrote:
Il 2012-12-23 07:42 Bruce Griffiths ha scritto:
The classic TAC using current mode switching is similar to the
attached circuit schematic.
I have a couple of small questions about this circuit.
Why are Q2 and Q13 driven by Vth? As there are inverted versions
of the Discharge and Ramp signals available, wouldn't it make sense
to use those to drive Q2 and Q13? I guess it would enhance switching
speed.
What is the reason behind the emitter followers Q1 and Q9?
Respecitvely, why shouldnt R3/R4, R7/R8 be connected directly to V+/V-?
Is there a special reson why the current source around Q9 is set to 20mA
and the one around Q4 to 10mA? Is it because Q14/Q15 are driven by a 20mA
current source while Q18/Q19 by a 10mA source?
Am i correct, that the only current source whos value really matters is
the one around Q11? If so, wouldn't it be beneficial to use a stable
reference voltage (probably coupled with the ADC reference) to be used
in an opamp based current source against GND or V- and a current mirror
(cascode or wilson) to drive Q18/Q19 (while leaving the other LED based
current sources as they are, including Q16)?
Attila Kinali
--
There is no secret ingredient
-- Po, Kung Fu Panda
On Thu, 3 Jan 2013 21:28:17 +0100
Attila Kinali attila@kinali.ch wrote:
What is the reason behind the emitter followers Q1 and Q9?
Respecitvely, why shouldnt R3/R4, R7/R8 be connected directly to V+/V-?
Scratch that question. Looking at the schematics again, it became obvious.
Attila Kinali
--
There is no secret ingredient
-- Po, Kung Fu Panda
Attila Kinali wrote:
On Sun, 23 Dec 2012 22:45:40 +0100
Fabio EboliFabioEb@quipo.it wrote:
Il 2012-12-23 07:42 Bruce Griffiths ha scritto:
The classic TAC using current mode switching is similar to the
attached circuit schematic.
I have a couple of small questions about this circuit.
Why are Q2 and Q13 driven by Vth? As there are inverted versions
of the Discharge and Ramp signals available, wouldn't it make sense
to use those to drive Q2 and Q13? I guess it would enhance switching
speed.
Only if the 2 complementary signals have closely matching propagation
delays.
This is usually true with ECL logic but not necessarily true with CMOS
logic.
Also the reverse emitter base breakdown voltage of faster transistors
will be exceeded with 10V pp differential drive.
What is the reason behind the emitter followers Q1 and Q9?
Respecitvely, why shouldnt R3/R4, R7/R8 be connected directly to V+/V-?
Avoidance of saturation and ensuring sufficent headroom for the current
sources/sinks.
Is there a special reson why the current source around Q9 is set to 20mA
and the one around Q4 to 10mA? Is it because Q14/Q15 are driven by a 20mA
current source while Q18/Q19 by a 10mA source?
No special reason although if the long tailed pair driving a subsequent
longtailed pair has a significantly lower tail current than the driven
pair the second pair will switch more slowly.
Am i correct, that the only current source whos value really matters is
the one around Q11? If so, wouldn't it be beneficial to use a stable
reference voltage (probably coupled with the ADC reference) to be used
in an opamp based current source against GND or V- and a current mirror
(cascode or wilson) to drive Q18/Q19 (while leaving the other LED based
current sources as they are, including Q16)?
Ideally the discharge switch current source should equal twice the
charge switch current source to ensure equal currents (and ideally equal
voltage drops across) in the clamp diodes when the ramp capacitor is
fully discharged..
A mirror uses extra matched transistors that can be avoided if an opamp
and reference is used to replace the LED's together with resistor
isolated feedback from the current source emitter.
The ADC reference isn't always accessible particularly with an ADC
embedded within a microprocessor.
Attila Kinali
Bruce