[CITASA] Contents of the latest issue of IJERTCS

SV
Seppo Virtanen
Thu, Dec 1, 2011 11:03 AM

The contents of the latest issue of:

International Journal of Embedded and Real-Time Communication Systems
(IJERTCS)
Official Publication of the Information Resources Management Association
Volume 2, Issue 4, October-December 2011
Published: Quarterly in Print and Electronically
ISSN: 1947-3176 EISSN: 1947-3184
Published by IGI Publishing, Hershey-New York, USA
www.igi-global.com/ijertcs

Editor-in-Chief: Seppo Virtanen, University of Turku, Finland

Special Issue: System-on-Chip

GUEST EDITORIAL PREFACE

“Special Issue on System-on-Chip”

Jari Nurmi, Tampere University of Technology, Finland
Seppo Virtanen, University of Turku, Finland

To read the preface, click on the link below, and then click on
"Preface" in the 4th Quarter issue.
http://www.igi-global.com/journal/international-journal-embedded-real-time/1162

PAPER ONE

Self-Calibrating Source Synchronous Communication for Delay Variation
Tolerant GALS Network-on-Chip Design

Alessandro Strano (University of Ferrara, Italy)
Carles Hernández (Universidad Politécnica de Valencia, Spain)
Federico Silla (Universidad Politécnica de Valencia, Spain)
Davide Bertozzi (University of Ferrara, Italy)

Source synchronous links for use in multi-synchronous networks-on-chip
(NoCs) are becoming the most vulnerable points for correct network
operation and must be safeguarded against intra-link delay variations
and signal misalignments. The intricacy of matching link net attributes
during placement and routing and the growing role of process parameter
variations in nanoscale silicon technologies are the root causes for
this. This article addresses the challenge of designing a process
variation and layout mismatch tolerant link for synchronizer-based GALS
NoCs by implementing a self-calibration mechanism. A variation detector
senses the variability-induced misalignment between data lines with
themselves and with the transmitter clock routed with data in source
synchronous links. A suitable delayed replica of the transmitter clock
is then selected for safe sampling of misaligned data. The manuscript
proves robustness of the link in isolation with respect to a
detector-less link, but also assesses integration issues with the
downstream synchronizer and switch architecture, proving the benefits in
a realistic experimental setting for cost-effective NoCs.

To obtain a copy of the entire article, click on the link below.
http://www.igi-global.com/article/self-calibrating-source-synchronous-communication/60151

PAPER TWO

Checkpointing SystemC-Based Virtual Platforms

Stefan Kraemer (RWTH Aachen University, Germany)
Rainer Leupers (RWTH Aachen University, Germany)
Dietmar Petras (Synopsys Inc., Germany)
Thomas Philipp (Synopsys Inc., Germany)
Andreas Hoffmann (Synopsys Inc., Germany)

The ability to restore a virtual platform from a previously saved
simulation state can considerably shorten the typical edit-compile-debug
cycle for software developers and therefore enhance productivity. For
SystemC based virtual platforms (VP), dedicated checkpoint/restore (C/R)
solutions are required, taking into account the specific characteristics
of such platforms. Apart from restoring the simulation process from a
checkpoint image, the proposed checkpoint solution also takes care of
re-attaching debuggers and interactive GUIs to the restored virtual
platform. The checkpointing is handled automatically for most of the
SystemC modules, only the usage of host OS resources requires user
provision. A process checkpointing based C/R has been selected in order
to minimize the adaption required for existing VPs at the expense of
large checkpoint sizes. This drawback is overcome by introducing an
online compression to the checkpoint process. A case study based on the
SHAPES Virtual Platform is conducted to investigate the applicability of
the proposed framework as well as the impact of checkpoint compression
in a realistic system environment.

To obtain a copy of the entire article, click on the link below.
http://www.igi-global.com/article/checkpointing-systemc-based-virtual-platforms/60152

PAPER THREE

International Symposium on System-on-Chip 2010

Jari Nurmi (Tampere University of Technology, Finland)

International Symposium on System-on-Chip 2010 was the 12th SoC event in
Tampere, Finland. The theme of this symposium was Embedded
Multi-processor/multi-core Computation Platforms. That was reflecting
the increasing interest in multicore and many core implementations on
System-on-Chip. This paper discusses briefly the history of the event
which is technically co-sponsored by IEEE Circuits and Systems Society.
The main focus is in an overview of the year 2010 contents, and in
particular in its tutorial and invited talks.

To obtain a copy of the entire article, click on the link below.
http://www.igi-global.com/article/international-symposium-system-chip-2010/60153

PAPER FOUR

Asymmetric Geographic Forwarding

Pramita Mitra (University of Notre Dame, USA)
Christian Poellabauer (University of Notre Dame, USA)

Geographic Forwarding (GF) algorithms typically employ a neighbor
discovery method to maintain a neighborhood table that works well only
if all wireless links are symmetric. Recent experimental research has
revealed that the link conditions in realistic wireless networks vary
significantly from the ideal disk model and a substantial percentage of
links are asymmetric. Existing GF algorithms fail to consider asymmetric
links in neighbor discovery and thus discount a significant number of
potentially stable routes with good one-way reliability. This paper
introduces Asymmetric Geographic Forwarding (A-GF), which discovers
asymmetric links in the network, evaluates them for stability (e.g.,
based on mobility), and uses them to obtain more efficient and shorter
routes. A-GF also successfully identifies transient asymmetric links and
ignores them to further improve the routing efficiency. Comparisons of
A-GF to the original GF algorithm and another related symmetric routing
algorithm indicate a decrease in hop count (and therefore latency) and
an increase in successful route establishments, with only a small
increase in overhead.

To obtain a copy of the entire article, click on the link below.
http://www.igi-global.com/article/asymmetric-geographic-forwarding/60154


For full copies of the above articles, check for this issue of the
International Journal of Embedded and Real-Time Communication Systems
(IJERTCS) in your institution's library.  This journal is also included
in the IGI Global aggregated "InfoSci-Journals" database:
http://www.igi-global.com/EResources/InfoSciJournals.aspx.


CALL FOR PAPERS

Mission of IJERTCS:

The mission of the International Journal of Embedded and Real-Time
Communication Systems (IJERTCS) is to disseminate recent advancements
and innovations in this interdisciplinary research area for field
researchers, practitioners, scientists, academicians, students, and IT
professionals. IJERTCS focuses on overcoming challenges involved in the
rapid development of embedded communication systems towards feature-rich
multimedia computers

Coverage of IJERTCS:

The International Journal of Embedded and Real-Time Communication
Systems (IJERTCS) extensively covers research in the area of embedded
and real-time communication systems. Within this field, topics to be
discussed in the journal include (but are not limited to) the following:

Asynchronous and synchronous circuit techniques
Design methods
Embedded networks (built-in networks in embedded communication devices)
Emerging new topics
Fault-tolerant hardware and software technologies
Formal design and verification methods
Hardware and software solutions for protocol processing
Hardware and software solutions for real-time systems
Hardware platforms and technologies
Hardware/software co-design
Modeling and verification methods
On-chip communication in SoC and NoC
OWA (open wireless architecture)
Performance modeling
Platform based design
Real-time computing
Reconfigurable systems
Security issues and technologies
Single-chip SDR (software defined radio) solutions
Software design
Testing techniques

Interested authors should consult the journal's manuscript submission
guidelines at www.igi-global.com/ijertcs

All inquiries and submissions should be sent to:
Editor-in-Chief: Seppo Virtanen at seppo.virtanen@utu.fi

The contents of the latest issue of: International Journal of Embedded and Real-Time Communication Systems (IJERTCS) Official Publication of the Information Resources Management Association Volume 2, Issue 4, October-December 2011 Published: Quarterly in Print and Electronically ISSN: 1947-3176 EISSN: 1947-3184 Published by IGI Publishing, Hershey-New York, USA www.igi-global.com/ijertcs Editor-in-Chief: Seppo Virtanen, University of Turku, Finland Special Issue: System-on-Chip GUEST EDITORIAL PREFACE “Special Issue on System-on-Chip” Jari Nurmi, Tampere University of Technology, Finland Seppo Virtanen, University of Turku, Finland To read the preface, click on the link below, and then click on "Preface" in the 4th Quarter issue. http://www.igi-global.com/journal/international-journal-embedded-real-time/1162 PAPER ONE Self-Calibrating Source Synchronous Communication for Delay Variation Tolerant GALS Network-on-Chip Design Alessandro Strano (University of Ferrara, Italy) Carles Hernández (Universidad Politécnica de Valencia, Spain) Federico Silla (Universidad Politécnica de Valencia, Spain) Davide Bertozzi (University of Ferrara, Italy) Source synchronous links for use in multi-synchronous networks-on-chip (NoCs) are becoming the most vulnerable points for correct network operation and must be safeguarded against intra-link delay variations and signal misalignments. The intricacy of matching link net attributes during placement and routing and the growing role of process parameter variations in nanoscale silicon technologies are the root causes for this. This article addresses the challenge of designing a process variation and layout mismatch tolerant link for synchronizer-based GALS NoCs by implementing a self-calibration mechanism. A variation detector senses the variability-induced misalignment between data lines with themselves and with the transmitter clock routed with data in source synchronous links. A suitable delayed replica of the transmitter clock is then selected for safe sampling of misaligned data. The manuscript proves robustness of the link in isolation with respect to a detector-less link, but also assesses integration issues with the downstream synchronizer and switch architecture, proving the benefits in a realistic experimental setting for cost-effective NoCs. To obtain a copy of the entire article, click on the link below. http://www.igi-global.com/article/self-calibrating-source-synchronous-communication/60151 PAPER TWO Checkpointing SystemC-Based Virtual Platforms Stefan Kraemer (RWTH Aachen University, Germany) Rainer Leupers (RWTH Aachen University, Germany) Dietmar Petras (Synopsys Inc., Germany) Thomas Philipp (Synopsys Inc., Germany) Andreas Hoffmann (Synopsys Inc., Germany) The ability to restore a virtual platform from a previously saved simulation state can considerably shorten the typical edit-compile-debug cycle for software developers and therefore enhance productivity. For SystemC based virtual platforms (VP), dedicated checkpoint/restore (C/R) solutions are required, taking into account the specific characteristics of such platforms. Apart from restoring the simulation process from a checkpoint image, the proposed checkpoint solution also takes care of re-attaching debuggers and interactive GUIs to the restored virtual platform. The checkpointing is handled automatically for most of the SystemC modules, only the usage of host OS resources requires user provision. A process checkpointing based C/R has been selected in order to minimize the adaption required for existing VPs at the expense of large checkpoint sizes. This drawback is overcome by introducing an online compression to the checkpoint process. A case study based on the SHAPES Virtual Platform is conducted to investigate the applicability of the proposed framework as well as the impact of checkpoint compression in a realistic system environment. To obtain a copy of the entire article, click on the link below. http://www.igi-global.com/article/checkpointing-systemc-based-virtual-platforms/60152 PAPER THREE International Symposium on System-on-Chip 2010 Jari Nurmi (Tampere University of Technology, Finland) International Symposium on System-on-Chip 2010 was the 12th SoC event in Tampere, Finland. The theme of this symposium was Embedded Multi-processor/multi-core Computation Platforms. That was reflecting the increasing interest in multicore and many core implementations on System-on-Chip. This paper discusses briefly the history of the event which is technically co-sponsored by IEEE Circuits and Systems Society. The main focus is in an overview of the year 2010 contents, and in particular in its tutorial and invited talks. To obtain a copy of the entire article, click on the link below. http://www.igi-global.com/article/international-symposium-system-chip-2010/60153 PAPER FOUR Asymmetric Geographic Forwarding Pramita Mitra (University of Notre Dame, USA) Christian Poellabauer (University of Notre Dame, USA) Geographic Forwarding (GF) algorithms typically employ a neighbor discovery method to maintain a neighborhood table that works well only if all wireless links are symmetric. Recent experimental research has revealed that the link conditions in realistic wireless networks vary significantly from the ideal disk model and a substantial percentage of links are asymmetric. Existing GF algorithms fail to consider asymmetric links in neighbor discovery and thus discount a significant number of potentially stable routes with good one-way reliability. This paper introduces Asymmetric Geographic Forwarding (A-GF), which discovers asymmetric links in the network, evaluates them for stability (e.g., based on mobility), and uses them to obtain more efficient and shorter routes. A-GF also successfully identifies transient asymmetric links and ignores them to further improve the routing efficiency. Comparisons of A-GF to the original GF algorithm and another related symmetric routing algorithm indicate a decrease in hop count (and therefore latency) and an increase in successful route establishments, with only a small increase in overhead. To obtain a copy of the entire article, click on the link below. http://www.igi-global.com/article/asymmetric-geographic-forwarding/60154 ***************************************************** For full copies of the above articles, check for this issue of the International Journal of Embedded and Real-Time Communication Systems (IJERTCS) in your institution's library. This journal is also included in the IGI Global aggregated "InfoSci-Journals" database: http://www.igi-global.com/EResources/InfoSciJournals.aspx. ***************************************************** CALL FOR PAPERS Mission of IJERTCS: The mission of the International Journal of Embedded and Real-Time Communication Systems (IJERTCS) is to disseminate recent advancements and innovations in this interdisciplinary research area for field researchers, practitioners, scientists, academicians, students, and IT professionals. IJERTCS focuses on overcoming challenges involved in the rapid development of embedded communication systems towards feature-rich multimedia computers Coverage of IJERTCS: The International Journal of Embedded and Real-Time Communication Systems (IJERTCS) extensively covers research in the area of embedded and real-time communication systems. Within this field, topics to be discussed in the journal include (but are not limited to) the following: Asynchronous and synchronous circuit techniques Design methods Embedded networks (built-in networks in embedded communication devices) Emerging new topics Fault-tolerant hardware and software technologies Formal design and verification methods Hardware and software solutions for protocol processing Hardware and software solutions for real-time systems Hardware platforms and technologies Hardware/software co-design Modeling and verification methods On-chip communication in SoC and NoC OWA (open wireless architecture) Performance modeling Platform based design Real-time computing Reconfigurable systems Security issues and technologies Single-chip SDR (software defined radio) solutions Software design Testing techniques Interested authors should consult the journal's manuscript submission guidelines at www.igi-global.com/ijertcs All inquiries and submissions should be sent to: Editor-in-Chief: Seppo Virtanen at seppo.virtanen@utu.fi