Magnus wrote

We don't quite agree on that point yet.
I can not find anything different or special that your code example is doing
"at it's output",
It seems to produce the exact same results as a standard PI controller.
Also in your code and all PI code the FLL function you talk about is
provided by the P term, Don't need to add the derivate, scale-factor F and
integrate term.

The derivate & integrate function could remove (or change) the signal's
offset if it was coded to do so,
But in your code, DC offset removal is not shown, so it would appear that
no  DC offset is being removed.
The DC Offset that is removed depends on what value that Vdp_pre is
initialize to, before the first cycle thru the code.
If Vdp_pre and Vi are both initialized to zero then there is no offset
removed,
and derivate, scale-factor_F then integrate exactally equals the same as
scale-factor_F only.
If vdp_pre is initalized to the first input value Vdp(0) instead of zero, as
is often the case, then the offset removed would be scale-factor_F x Vdp(0)

either way the code (with Vdp_pre & Vi pre-initialized to zero)

appears to produces the exact same output as the simpler code:
(when Vi is initalized to zero)

Vi = Vi +  (I * Vdp)  ;
Vf = Vi + (P+F) * Vdp

(To add offset removal, Initialize Vi to - F * First_Vdp_reading )

Also get same results from: (where Dc  =  0)
or for offset removal set Dc  to F*First_Vdp_reading

Vi = Vi +  (I * Vdp)
Vf = Vi + (P+F) * Vdp -  Dc

We're going to have to disagree on that also.
The output is the sum of the P term and the I term, You end up with the
exact same results if you take something away from one of then and apply it
to the other.
That is what my two code examples are doing.
If you want faster pull in just increase the product of F*P, it does not
matter which, They both give the same exact results for DC and AC.

Tom, do you want to program Gpsim1 to break this standoff?

ws

Warren,

On 12/04/14 21:09, WarrenS wrote:

I may appear so, but the derivate, scale-factor F and integrate does not
make the scale-factor F equalent to P, since you are forgetting that the
derivate removes the DC term and the integration forms it's own DC term.
This DC-term as scaled through oscillator gain and added to the
oscillators offset is then subtracted from the reference frequency and
thus the error frequency is input to the integrator stage.

The FLL variant model can be understood if the differentiation is pushed
to both inputs of the phase comparator, where the reference frequency
and oscillators frequency will be subtracted rather than their phase and
the only remaining integrator in the loop is that holding the Vi term.
The frequency error term will exponentially decay with the time-constant
as set by the F coefficient.

So, F and P is not equivalents, as P will not contribute to the state of
Vi, which is evident in the weak pull-in of a standard PI loop.

However, F and P will for the AC behaviour of the loop be equivalents,
so care must be taken into setting P with regard to F in order to get
the expected damping of the loop.

Anyway, this is a FLL-aided PI-loop, which looks like an incorrectly
wired PID-loop. Quite minimalistic.

I think I covered that above.

It is missing a whole deal, but I wanted to illustrate the core.
One thing which is not covered is the un-wrapping of the phase detector
in the case that it does not wrap around binary. Another thing, the
frequency detector phase history may need to be unwrapped prior to
subtraction in order to make sure the frequency estimate becomes correct.

I avoided the "D" coefficient name as it will be confusing to a normal
PID naming, when it will in fact does not do the normal "D".

Cheers,
Magnus

Warren,

On 13/04/14 07:44, WarrenS wrote:

You are over-focusing on the derivate canceling the integrate of the
loop-state, but if you want to play that game and make sense out of it,
you should not cancel out the integrator in the PI operation, but the
integrators of the reference (resulting in omega_0) and that of the
steered oscillator (resulting in omega_0 + omega_e + KoVf). As they go
through the phase comparator (really a frequency comparator) you have
Kd(omega_0 - (omega_0 - omega_e)) = -Kdomega_e -KdKo*Vf. That is then
scaled by the F factor into the integrator and the integrator then
alters it's state to cancel this out. This is happening when frequency
error (omega_e - it's angular frequency variant) is so large that the
PLL part is beating and has almost no DC component to charge the
integrator with. The P factor will simply not aid in building up the
integrator state like this.

So, that part is a FLL.

I know it is confusing, but one has to see the complete loop, and see
how you can aid in bulding up the frequency correction state. PLLs is
really bad at this if the error is large. FLL aiding that state buildup
helps a lot.

Once you have started to understand the double nature of this loop, it's
FLL and PLL styles you also realize that the FLL part degrades itself
into a contributor to the AC-components proportional path, as the
frequency error component has a zero DC component. However, if the loop
is put into stress, the FLL starts aiding on the frequency again. There
is thus no "mode" but rather "dominant characteristics" and depending on
the frequency error of the loop either the FLL or PLL is dominant.

Cheers,
Magnus