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BP

Brian Padalino

Tue, Mar 11, 2025 8:47 PM

I am trying to add a timekeeper listener, axi_mm memory interface, and a
pps interface using rfnoc_modtool with the yml description and it doesn't
seem like it actually adds the ports to the top level when the code is
being generated.

I verified this by using the replay.yml block in an OOT and it only seems
to create the chdr, ctrl, and adds the mem_clk input.

Is this a known issue? Am I doing something wrong?

Sorry for the confusion.

Thanks,
Brian

I am trying to add a timekeeper listener, axi_mm memory interface, and a pps interface using rfnoc_modtool with the yml description and it doesn't seem like it actually adds the ports to the top level when the code is being generated. I verified this by using the replay.yml block in an OOT and it only seems to create the chdr, ctrl, and adds the mem_clk input. Is this a known issue? Am I doing something wrong? Sorry for the confusion. Thanks, Brian

PN

Philipp Niedermayer

Wed, Mar 12, 2025 9:31 AM

It's a known issue from the time the tool was still called
"rfnoc_create_verilog" (but using the same templates).

Quote: "You did the right thing. The io_ports aren't currently supported
by rfnoc_create_verilog, so AXI ports have to be added manually."

See https://github.com/EttusResearch/uhd/issues/605

From: Brian Padalino bpadalino@gmail.com

Sent: Tuesday, 11 March 2025 at 21:47

To: USRP-users@lists.ettus.com usrp-users@lists.ettus.com

Subject: [USRP-users] rfnoc_modtool io_ports not being populated

I am trying to add a timekeeper listener, axi_mm memory interface, and
a pps interface using rfnoc_modtool with the yml description and it
doesn't seem like it actually adds the ports to the top level when the
code is being generated.

I verified this by using the replay.yml block in an OOT and it only
seems to create the chdr, ctrl, and adds the mem_clk input.

Is this a known issue? Am I doing something wrong?

Sorry for the confusion.

Thanks,
Brian

USRP-users mailing list --usrp-users@lists.ettus.com
To unsubscribe send an email tousrp-users-leave@lists.ettus.com

It's a known issue from the time the tool was still called "rfnoc_create_verilog" (but using the same templates). Quote: "You did the right thing. The io_ports aren't currently supported by rfnoc_create_verilog, so AXI ports have to be added manually." See https://github.com/EttusResearch/uhd/issues/605 *From:* Brian Padalino <bpadalino@gmail.com> *Sent:* Tuesday, 11 March 2025 at 21:47 *To:* USRP-users@lists.ettus.com <usrp-users@lists.ettus.com> *Subject:* [USRP-users] rfnoc_modtool io_ports not being populated > I am trying to add a timekeeper listener, axi_mm memory interface, and > a pps interface using rfnoc_modtool with the yml description and it > doesn't seem like it actually adds the ports to the top level when the > code is being generated. > > I verified this by using the replay.yml block in an OOT and it only > seems to create the chdr, ctrl, and adds the mem_clk input. > > Is this a known issue? Am I doing something wrong? > > Sorry for the confusion. > > Thanks, > Brian > > _______________________________________________ > USRP-users mailing list --usrp-users@lists.ettus.com > To unsubscribe send an email tousrp-users-leave@lists.ettus.com

MB

Martin Braun

Tue, Apr 8, 2025 8:24 AM

On Wed, Mar 12, 2025 at 10:32 AM Philipp Niedermayer p.niedermayer@gsi.de
wrote:

It's a known issue from the time the tool was still called
"rfnoc_create_verilog" (but using the same templates).

Quote: "You did the right thing. The io_ports aren't currently supported
by rfnoc_create_verilog, so AXI ports have to be added manually."

See https://github.com/EttusResearch/uhd/issues/605

This is all correct. We're slowly (I know, too slowly for some) adding such
features to the RFNoC tooling.

--M

On Wed, Mar 12, 2025 at 10:32 AM Philipp Niedermayer <p.niedermayer@gsi.de> wrote: > It's a known issue from the time the tool was still called > "rfnoc_create_verilog" (but using the same templates). > > Quote: "You did the right thing. The io_ports aren't currently supported > by rfnoc_create_verilog, so AXI ports have to be added manually." > > See https://github.com/EttusResearch/uhd/issues/605 > This is all correct. We're slowly (I know, too slowly for some) adding such features to the RFNoC tooling. --M