From: "usrp-users-request@lists.ettus.com" <usrp-users-request@lists.ettus.com>

 self.uhd_usrp_source_0.set_time_next_pps(uhd.time_spec(0))
 self.uhd_usrp_source_1.set_time_next_pps(uhd.time_spec(0))
 time.sleep(1.0)

 start_time = uhd.time_spec(5.0)
 self.uhd_usrp_source_0.set_start_time(start_time)
 self.uhd_usrp_source_1.set_start_time(start_time)

Thankx for the info Martin. By any chance, does anybody have a copy of old USRP1 Rev2 schematics?The one available for download is for USRP1 Rev3 or 4+... Angilberto.  From: "usrp-users-request@lists.ettus.com" <usrp-users-request@lists.ettus.com> To: usrp-users@lists.ettus.com Sent: Thursday, October 26, 2017 1:40 PM Subject: USRP-users Digest, Vol 86, Issue 25 Send USRP-users mailing list submissions to     usrp-users@lists.ettus.com To subscribe or unsubscribe via the World Wide Web, visit     http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com or, via email, send a message with subject or body 'help' to     usrp-users-request@lists.ettus.com You can reach the person managing the list at     usrp-users-owner@lists.ettus.com When replying, please edit your Subject line so it is more specific than "Re: Contents of USRP-users digest..." Today's Topics:   1. 2 B210 synchronous problem (Hideyuki Matsunaga)   2. B210 -- various questions on sampling/clock rates (Rob Heig)   3. Re: FLEX900 + USRP1 Rev2 (Martin Braun)   4. Re: systemverilog files in rfnoc block (Dario Pennisi)   5. Re: systemverilog files in rfnoc block (Jade Anderson)   6. Re: B210 -- various questions on sampling/clock rates       (Anon Lister)   7. Re: 2 N200 MIMO system phase offset varies with frequency,       have used timed_command with tune and also integer-N Tuning per       Marcus M post of Feb 17, 2016 (John Shields)   8. USRP B210 time errors with high master clock rate       (Perelman, Nathan)   9. Re: B210 -- various questions on sampling/clock rates (Rob Heig)   10. performance_data for TwinRx (liu Jong)   11. B205mini: 0-value Samples When Switching Center Frequency       (Gilad Beeri (ApolloShield))   12. cross-compiling with external libraries on E310 (Francois Quitin)   13. Re: cross-compiling with external libraries on E310       (Philip Balister)   14. Re: cross-compiling with external libraries on E310       (Francois Quitin)   15. Re: cross-compiling with external libraries on E310       (Philip Balister)   16. Re: B205mini: 0-value Samples When Switching Center Frequency       (Marcus D. Leech)   17. Re: [Discuss-gnuradio] Extra RF shielding? (Marcus M?ller)   18. Re: Advise on how to modifying HDL design E310 to add custom       blocks (Derek Kozel) ---------------------------------------------------------------------- Message: 1 Date: Wed, 25 Oct 2017 15:59:39 +0900 From: Hideyuki Matsunaga <hideyuki.matsunaga@gmail.com> To: usrp-users@lists.ettus.com Subject: [USRP-users] 2 B210 synchronous problem Message-ID:     <CA+HAK=qcXCr7ymvF8XWB5i2Kmmn2+o1TEtb60dt7OspGrD+jJA@mail.gmail.com> Content-Type: text/plain; charset="utf-8" Hi I bought 2 B210s for testing direction of arrival estimation, like below. =======================  Configuration ============================= Ch0 <--> | USRP0 Rx 0 |         |            | <-- USB3.0 --> |      PC                        | Ch1 <--> | USRP0 Rx 1 |                | Ubuntu 14.04                    |                                       | GNU Radio Companion 3.7.11.1    | Ch2 <--> | USRP1 Rx 0 |                | UHD_003.010.001.001-79-g7ac01c7f|         |            | <-- USB3.0 --> |                                | Ch3 <--> | USRP1 Rx 1 | - External 10MHz reference CLK & 1PPS are provided by function generator(Tektronix AFG1012) to each B210 - center freq  2.4GHz - samping rate 4MHz In GRC - 2 separate USRP Source for each B210, settings are below - Sync option  unknown pps - Clock Source  External - Time Source  External - Num Channels  2 I generated python code by GRC and then I added custom timing adjustment code. ``` self.uhd_usrp_source_0.set_time_next_pps(uhd.time_spec(0)) self.uhd_usrp_source_1.set_time_next_pps(uhd.time_spec(0)) time.sleep(1.0) start_time = uhd.time_spec(5.0) self.uhd_usrp_source_0.set_start_time(start_time) self.uhd_usrp_source_1.set_start_time(start_time) ``` =========================================================================== I believe that I am following all the instructions what I found in web. but, when I tried to check that sampling timing is exactly matched or not by dumping all the samples(connect File Sink), I found sampling gaps between 2 B210. While testing, I confirmed that - there are no overflow, - start timing would be exactly the same(using Tag Debug to confirm) I observed that - gaps looks fixed size during running - gaps are slightly different every time Please let me know what I am missing. Thanks, Matsu