Dear Community, I'm working with the Ettus USRP X3x0 series, specifically the X310, and have encountered challenges due to missing schematic pages—particularly page 13, which is not publicly available. I'm trying to understand the connections related to the DB_DAC_*** signals. From my investigation, it appears these signals are connected to Bank 18 of the FPGA and are configured as LVCMOS18. Unfortunately, detailed information about these connections seems to be on the missing schematic pages. I understand that these pages are often associated with the PCIe interface, but the DB_DAC_*** signals don't seem to be directly related to PCIe functionality. Therefore, I'm reaching out to see if anyone in the community can provide insights or guidance on accessing or understanding the connections to FPGA Bank 18, especially concerning the DB_DAC_*** signals. Any assistance or pointers to relevant documentation would be greatly appreciated.

Rabih, It might help if you asked the question more directly: What is it you need to understand relating to the DB_DAC_* signals? They are the digital pins connecting the digital-to-analog converters to the FPGA. If you are just looking for pin assignments, they can be found in the UHD repository here <https://github.com/EttusResearch/uhd/blob/master/fpga/usrp3/top/x300/x300.xdc> . Nick On Mon, Jun 2, 2025 at 1:14 PM Rabih Nouraldine <Rabih@humanitas.io> wrote: > Dear Community, > I'm working with the Ettus USRP X3x0 series, specifically the X310, and > have encountered challenges due to missing schematic pages—particularly > page 13, which is not publicly available. > I'm trying to understand the connections related to the DB_DAC_*** signals. > From my investigation, it appears these signals are connected to Bank 18 of > the FPGA and are configured as LVCMOS18. Unfortunately, detailed > information about these connections seems to be on the missing schematic > pages. > I understand that these pages are often associated with the PCIe > interface, but the DB_DAC_*** signals don't seem to be directly related > to PCIe functionality. Therefore, I'm reaching out to see if anyone in the > community can provide insights or guidance on accessing or understanding > the connections to FPGA Bank 18, especially concerning the DB_DAC_*** > signals. > Any assistance or pointers to relevant documentation would be greatly > appreciated. > _______________________________________________ > USRP-users mailing list -- usrp-users@lists.ettus.com > To unsubscribe send an email to usrp-users-leave@lists.ettus.com >