Hi

Is your intended application tolerant of spurs at 16 and 32 MHz? If not, do they need to be in the 90 dB down vicinity (= the SFDR of the ADC) ?

Bob

Hi,

On 2020-01-19 01:28, Mark Haun wrote:

You should be able to do exactly that.

You do not need very high Q, as suitable LCR will fit. Besides, if there
is any of the other overtones creating issues, you can build LCR links
tuned to these that will consume that energy.

The other fairly obvious solution is as already suggested by Bert is to
use a SiLabs chip. You can get a test-board and test this easy, in fact,
several boards exists which is ridicolously cheap. There is one from QRP
labs which has additional filtering on power to have less noise issues.
It lies there on my lab-bench assembled, but I have yet to measure it.

Regardless if which solution you try, what capability do you have to
test it? It remains an important tool here. There is no golden design
that just solves everything. I've recently measured how very well
performing devices performance was partly lost due to bad design. I use
the old and trusty TimePod.

Cheers,
Magnus

Hi Magnus,

On Sun, 19 Jan 2020 15:56:37 +0100
Magnus Danielson magnus@rubidium.se wrote:

Thanks, this makes sense.  Any general suggestions for the active
device selection, and circuit topology?  Is the common-base BJT circuit
(in the archive link) a good starting point?

I think Bert was referring to the ICS570 rather the the Si570.  The ICS
part would completely destroy the sub-picosecond jitter performance of
my oscillator (datasheet quotes jitter on the order of 100 ps!), so is
not an option.  The Si570 family is interesting.  I had another look at
the jitter / phase-noise specs and it probably would be good enough for
an 80-MSPS ADC.  However, I have other reasons (longer-term stability)
for wanting to use the OCXO.

Aha, this is the elephant in the room...  I will confess, I was hoping
for some rules of thumb that would give me 90% confidence without
having to validate the design.  (It's a hobby project, so a certain
amount of risk-taking is OK.)

The only time/freq stuff I have currently are a couple of HP 53310A
analyzers and a Trueposition GPSDO.  Putting together a DMTD setup
would be fun but my project queue is already overflowing :)

Regards,
Mark

Hi Bob,

On Sun, 19 Jan 2020 09:37:39 -0500
Bob kb8tq kb8tq@n1k.org wrote:

I guess you mean stray coupling between the oscillator, clock
conditioning circuitry and the analog inputs?  (Spurs on the ADC clock
input shouldn't matter as long as the zero crossings are clean and
jitter is low.)

This would be for a direct-sampling HF (shortwave) radio.  A few extra
spurs are OK, especially synchronous ones like these which you could
theoretically subtract in the digital domain.

Regards,
Mark

On 1/19/20 9:29 AM, Mark Haun wrote:

Not exactly.  The sampler of the ADC is essentially a mixer, so if the
clock has other signals on it, even at low levels, they can mix with
input signals and show up in band.  I had a SDR receiver with a 49.244
MHz ADC clock that was contaminated by the 66MHz processor clock (at a
very, very low level), and I saw mixing products when the input to the
ADC was a clean sine wave at 112.5 MHz.

Analog Devices even has an app note on this.

https://e2echina.ti.com/cfs-file/__key/telligent-evolution-components-attachments/13-109-00-00-00-00-93-58/Impact-of-sampling_2D00_clock-spurs-on-ADC-performance.pdf

Don't forget to consider high order multiples of the interfering clock,
too, that might mix and alias down into your sampling bandwidth.

You may also need to bandlimit your clock input - since noise on the
clock mixes with the input. This is often a problem when you have a fast
wideband clock buffer in front of the ADC clock input - that buffer's
noise can mix with the input signals.

https://www.analog.com/media/en/technical-documentation/application-notes/AN-756.pdf

https://www.analog.com/media/en/technical-documentation/application-notes/AN-1067.pdf

Hi Jim,

On Sun, 19 Jan 2020 10:35:42 -0800
jimlux jimlux@earthlink.net wrote:

Hmmm, so in my case, other residual odd-order harmonics of the 16 MHz
input clock which make it through the multiplier will become
non-harmonic spurs of the desired 80 MHz, and therefore a potential
problem unless filtered out.  The analog amplifier scheme will
therefore require decent bandpass filtering, mainly against 16, 48, and
112 MHz.

One advantage of the Wenzel CMOS-based multiplier is that the threshold
behavior of the last inverter [mostly?] gets rid of everything but the
selected harmonic.

I'm still trying to understand the phase-noise pros/cons of that design
using, say, a pair of NC7SZ04 (UHS family) gates, versus a discrete
transistor amplifier tuned at 80 MHz, like the common-base design
quoted in the original post.

Regards,
Mark

Hi Mark,

On 2020-01-19 18:19, Mark Haun wrote:

I have not checked. It's not very difficult, frequency select out the
right over, tone, provide gain without too much flicker noise and white
noise. Consider a diff-pair/long-tailed pair.

Other sub-tones needs to be suppressed enough to not alter transition
time too much as this would influence the jitter.

But the long-term would belong to the and the step in frequency would be
due to that chip.

I see. I try to recommend people to be able to measure phase noise and
stability,

You can come fairly long with a relatively trivial setup and ability to
measure spectrum.

A mixer, a PI-loop, an oscillator and then synthesis for coarse
frequency setting makes a loop that then just needs a spectrum analysis
with a bit of scaling to give you jitter. Home-brewing this should not
be too hard. Maybe it just lacks an example setup and some software
support. If one assumes offset frequencies up to 20 kHz, then the audio
ports can be used to sample and then FFT it, but many audio ports is
limited in the lower end of the spectrum, few go to DC. Yet, for the
relatively simplicity one can get started.

Oh, I need to be a little bit more specific than I was before, QRP labs
have a project called ProgRock, a fun little project. However, it does
not have an organized input, it's intended to operate on a 27 MHz
crystal. It is however an example of a cheap SiLabs project. The
ProgRock combines a simple CPU with the 5351 chip, where as often you
have a chip with basic support, but you need to program it from outside.

Cheers,
Magnus

the only problem with that CMOS  freq. multiplying circuit's that the
threshold of the inputs  has a thermal noise component = jitter [phase
noise]
73
KJ6UHN
Alex

On 1/19/2020 11:31 AM, Mark Haun wrote:

Hi Alex,

Well, all amplifiers will face that noise, but how it does it makes it
more or less an issue. Some digital inputs are better than others to
handle it, essentially by sub-sequent amplification stages, but most is
not fantastic at it. Wither it is the dominant source of noise or not
remains to be measured. This is where phase-noise measurement is such a
great tool for analysis, as ADEV smoothes things out to make it harder
to detect the root cause. This is why I say, measure phase-noise and
clean that up, before going to ADEV.

Cheers,
Magnus

On 2020-01-19 23:00, Alex Pummer wrote:

Am 19.01.20 um 22:20 schrieb Magnus Danielson:

It's not that the high Q circuit generates noise, it's more

that the phase runs away when the resonant frequency runs away.

For a minimum phase network, you have +- 45° at the -3 dB points.

Ha, that hurts! Sheer mockery! I have spent the entire weekend

trying to control my 89441A FFT analyzer from Linux via a

Prologix USB-to-IEEE488 dongle. Setting /dev/ttyUSB0 to raw

and getting rid of the buffering was easy. Telling if that !#&%§!!

Prologix thing terminates the strings to the computer with LF

or CRLF seems impossible to predict, in spite of a command to

set this. And there is no way to measure anything on that virtual

tty port to watch the traffic. Use of tees activates buffering, no

way around.

Typical Heisenbug. Observing it affects the outcome.

The idea was just to measure 1/f noise on my AF and RF transistors

in a circuit inspired by that in Art Of Electronics V3.

Good book. Must have.

I have cut out the output amplifier circuit of my OCXO support

board and removed the doubler option and the notch filter. It provides

22 dBm after a MV89A, enough for two ranks of power dividers in front

of the Timepod.  Transformers are still sub-optimum, esp. at the low end

and on the output side, but I wanted to avoid winding them myself.

DC emitter degeneration is 50 Ohm to fight 1/f, less than that above a

few 100 KHz as fits the gain. Push-pull common base.

A 10 MHz MV89A is internally 5 MHz, and you can see that in the spectrum.

External notch definitely required.

regards, Gerhard

Hi Gerhard,

On 2020-01-20 00:03, Gerhard Hoffmann wrote:

Yes, the steep phase-slopes makes any shift cause great phase-shifts,
which is another way of experiencing the group delay (= dphi/df), and
the amplitude of that is proportional to the Q of a resonance. The phase
is still 45 degrees at the -3 dB points, it's just that those is very close.

No mockery intended.

I would be very interested to do exactly that. I've actually had issues
getting the Prologix do things exactly as I want, and I blame that on my
inability to focus long enough to read the manual to understand it
properly. The lack of being able to debug the GPIB properly helps with
the confusion. I need to do more GPIB programming, and perferably in
Linux as I feel right at home there in general. One of my 89410s have
cross-correlator capabilities, and I have a bit of other goodies, so it
is about bringing things together.

That's not a bad starting-point if you only have that one book.

Now, which of the circuits did you get inspired from? I assume you where
using one of the Chapter 8 circuits.

Ah, so they double rather than build a 5 and a 10 MHz core oscillator.
There is some merits to that, and drawbacks.

I should have some of those lying around here somewhere.

Cheers,
Magnus

Hi

A very real question is — does this matter in the intended application?

If the task at hand is measuring ADEV over 1,000 to 100,000 seconds, then yes indeed
it will come into play. If the task is demodulation audio with a lower cutoff of 10Hz
then no its not going to matter in the least little bit. The “noise” from a tuned
circuit moving as the HVAC does it’s thing is very low frequency compared to
normal audio ….

Bob

Gerhard wrote:

Absolutely right.  But most electronics amateurs don't seem to want to
spend the money for what is arguably the most important tool available
to improve their understanding.  In my view, Chapter 8 alone ("Noise")
is worth the price all by itself ($80 at Amazon).

Speaking of price, I see Springer has a newish English edition of Tietze
& Schenk for over $900!!  I like my 1991 English edition just fine, but
for >$900 I expect it to actually build prototypes of the circuits it
shows!!  [Generally speaking, H&H is a better learning resource, IMO.
To call T&S a "cookbook" is an unwarranted put-down, but it is organized
more or less along those lines though with much additional explanation.
I see it more as a reference and refresher for those who already know
the material ("I seem to recall seeing a circuit that would do what I
need...") rather than getting students up the hump of the learning curve
in the first instance.]

For anyone who doesn't know yet, the long-awaited Horowitz & Hill "X
Chapters" is on pre-order now at Amazon ($54), expected to ship around
the end of January:

https://www.amazon.com/dp/1108499945

I have seen some of it, and as I expected, it is another must-have.

Best regards,

Charles

I got my  German edition of T+S [16] for $120.- shipped to California,
but don't be surprised some of the medicament's made in Europe costing
50 times more here.
73
KJ6UHN
Alex

On 1/19/2020 5:30 PM, Charles Steinmetz wrote:

Am 20.01.20 um 01:48 schrieb Magnus Danielson:

Not only proportional, that is the operating Q. And in some oscillators

it is easy to measure with the Randall-Hock correction for the
self-terminated

loop and an ordinary network analyzer. The RH-correction delivers the

exact loop gain of the cascade as if it was fed from its own output and

loaded by its own input, just from the s-parameters of the opened loop.

The oscillator works where phase(S21) goes through 0 and it helps
tremendously

if you can see that your optimum Q happens 30 Hz lower thanks to the tank

circuit or a mistuned spurious trap.

My 89410/41 has nearly all the options, including the RF box but one

thing I really miss is the ability to do logarithmic sweeps from mHz

to 1 MHz. It has the network option for BNC-Ethernet, and with a

BNC-RJ45 bridge from Amazon I could connect it to my LAN.

Then I could simply open port 5025 or so on 192.168.178.x and

feed it with SCPI strings. That actually worked quite good but

sometimes the 89441A would stop listening and nothing but a

power cycle would bring it back online.

The network access clearly missed things like "interface clear".

So my interface program got the option -488 and multiplexers

in open_89441(), close(), cmnd() and query_89441(). That was

the easy part. But for the state as of NOW I have just replaced

an unwilling tcp/ip socket with an unwilling Prologix dongle that

is even harder to bring into a known state.   :-(

My control program makes a FFT for each of the typically 7 decades

of interest, collects the data, adjusts for resolution BW and finally

calls gnuplot  to make nice .eps, .png and QT-terminal pictures.

I have also provided some access to cross correlation, but the results

are unreasonably good. My HP3325 does not have > 110 dB harmonics

suppression. But that is a minor problem once the interface is stable.

That's always a good book.

Like the Hobbits: They loved to have many books of things they understood...

Fig. 8.92.

I added a TL431 for the ability to pull the base/gate voltage down to -1V

for measuring FETs. That requires a polarity reversal switch for the

160000 uF base shorting capacitors. The bias pot needs a protection

resistor in case you turn it to the GND side with the capacitor charged.

One might wipe out the wiper otherwise. The -1V mod takes care of that

as a byproduct.

The capacitance multiplier did not help much. Just connecting that thing

to a R&S NGT20 power supply introduced a lot of GND loop noise.

I operate it from NiMH or Li cells.

I also added a cascode for RF performance and 3 stages of ADA4898 as

a post amplifier.

The test signal injection for gain measurement  goes through the bottom

side of the huge base capacitor. That is not directly connected to GND but

only through some MilliOhms. A 49R9 resistor from the test-signal-in-BNC

completes that to a 60 dB attenuator. One Volt of input gives 1 mV at
the base.

Just leave it open if not needed. I did not like the semi-floating BNC
in the

original design.

In the DUT base connection is an optional 60 Ohm resistor that provides an

1nV/rtHz voltage noise reference. It needed to be switched in / shorted out

by an SMD relay. Wiring this connection to a switch on the wall of the box

picked up way too much noise.

Pic: left is the cap multiplier, then the bias/DUT section, right side
5*33000 uF

base shorting cap. It is definitely needed that large if you want to
examine the 1/f region.

Cheers, Gerhard

On Mon, Jan 20, 2020 at 12:49 AM Magnus Danielson magnus@rubidium.se
wrote:

The open-source and cross-platform sigrok (https://sigrok.org/wiki/Main_Page)
capture/analysis tool has a protocol decoder for GPIB which will turn any
supported 16-bit logic analyser into a GPIB sniffer.

Recommended cheap capture tool is a Cyprus ez-usb dev board like
https://www.ebay.com/itm/223633738735

The Cyprus board can be wired directly to a GPIB connector but I've
produced a PCB that will adapt it to a pair of connectors for passthrough
use : you can obtain it from

https://oshpark.com/shared_projects/1FVMoqoQ

Unfortunately Oshpark are surprisingly expensive for that board but if
there's interest I'll happily put it on one of the chinese sharing sites
such as pcbway. I don't really want to get involved in stocking and
shipping them.

On Sat, 18 Jan 2020 16:28:56 -0800
Mark Haun mark@hau.nz wrote:

With those constraints, and reading the discussion, I wonder why don't
consider a VCXO+PLL solution. Using something like the Abracon ABLNO and
a generic PLL (e.g. ADF4001) would give you above performance. The ABLNO
are so low noise enough, that you can use a low BW loop filter (order of 500Hz)
and get lower output noise than the up-multiplied 16MHz signal above that
and the (multiplied) OCXO performance below that (with a slight bump due
to the PLL around the loop filter frequency).

The big advantage over the multiplier solution is that you don't have to
deal with a high level of harmonics and get a very clean signal with
almost no effort.

		Attila Kinali

--
Science is made up of so many things that appear obvious
after they are explained. -- Pardot Kynes

On Mon, 20 Jan 2020 11:13:46 +0100
Attila Kinali attila@kinali.ch wrote:

Addendum: I don't know your application, but in a general high-speed
sampling systems, it's the white noise floor that you are worried
about, not the 1/f^a noise. And in that case, having a lown noise XO
produce your sampling clock is better than multiplying a low frequency
OCXO and using this directly, even if the XO is free running.

		Attila Kinali

--
It is upon moral qualities that a society is ultimately founded. All
the prosperity and technological sophistication in the world is of no
use without that foundation.
-- Miss Matheson, The Diamond Age, Neal Stephenson

Hi Attila,

On Mon, 20 Jan 2020 14:29:15 +0100
Attila Kinali attila@kinali.ch wrote:

A fair question... in fact I was initially planning to use the ABLNO +
a PLL.  The OCXOs I found, however, are CTS VFOV405's with phase noise
claimed to be just as good as the ABLNO or CVHD VCXOs:
https://www.ctscorp.com/wp-content/uploads/VFOV405.pdf
They are reasonably low power, small[-ish], and have adequate stability
for my needs.  You can see why it is tempting to make the multiplier
scheme work, as it should save on both power and board area. (The
target application is a battery-powered SDR.)  So far there don't seem
to be any show-stopper issues with the plan, except that I am going to
have to put together a phase-noise measurement system, or find a friend
with one.

To that end, I wonder if something like Andrew Holme's project,
http://www.aholme.co.uk/PhaseNoise/Main.htm
is the best "bang for the buck" right now?  It looks like that could be
put together for well under $1k (minus the Wenzel ULN oscillator :).  A
simpler, sound-card-based approach is also appealing, but I have not
seen any ready-to-build projects published on the web, and I cannot
afford to put in the hundreds of hours it would take to design my own.

Regards,
Mark

Hi

If you are starting at 16 MHz and multiplying by 5, the phase noise will degrade
by 20 log (N). In this case, that will be 14 db. The degradation may be more than that,
but it can never be less.

Another issue is just how the spec’s actually apply. On any oscillator that is spec’d over a
range of frequencies, some may do a bit better than others. Will this device at that frequency
exceed the spec by 6 db? Will another model at the same frequency “only” exceed the spec
by one db? Without testing a bunch of them …. no way to know.

Bob

On Mon, 20 Jan 2020 13:13:00 -0500
Bob kb8tq kb8tq@n1k.org wrote:

Well, worse than that, the VFOV405 phase noise is a "typical" not a
"max" spec ;)  On the other hand, I should have some leeway at only 80
MSPS and no bandpass sampling.  (The main spectrum of interest is 5-20
MHz.)  I am aware of the 20logN relationship and that there will be some
residual extra phase noise from my multiplier on top of it.

The VFOV405 datasheet lists typical phase noise for 10- and 100-MHz
units.  (Mine are 16.384 MHz.)  In comparing the two oscillators, I have
used the 100-MHz "typical" numbers which they both state:

offset    VFOV405    ABLNO
10        -90        -88
100      -120      -118
1k        -140      -141
10k      -160      -160
100k      -163      -161

(The ABLNO also provides a worst-case spec which is 3-5 dB worse.)

Regards,
Mark

Hi

So taking the 14 db from multiplication into account:

	VFO405		ABLNO		

1K -126 -141
10K -146 -160
100K -149 -161

Looking at the plots on the ABLNO data sheets, the wide band noise gets
down a bit below -161 on a “typical” basis.

Locking an 80 MHz ABLNO to 16.384 is not going to be as easy as locking
one to 16.000. Getting an ABLNO with an EFC at 16.384 x 5 may be a bit of
a challenge.

Bob

On 1/20/20 10:01 AM, Mark Haun wrote:

Have you checked delivery times? - Just because it's listed in the
catalog does not mean you can get it in the next few weeks or months.
If the online sources (Digikey, mouser, Newark, etc.) have them in
stock, then you're good to go, but otherwise you could be looking at 6
months or more.

Hi

…. and maybe nasty stuff like minimum order quantities in the range of 10 or 20 pieces ( or prices below that which work out to the same thing).

Bob

On Mon, 20 Jan 2020 14:22:41 -0500
Bob kb8tq kb8tq@n1k.org wrote:

Agree except you were starting from the VFOV numbers for the 100-MHz
version.  If you use their numbers for the 10-MHz version and add 20 dB
for an ideal 10x multiplication, for comparing with the ABLNO spec at
100 MHz, you end up with

offset    VFOV405 @ 10M, ideal 10x multiply    ABLNO @ 100 M
10        -100                                  -88
100      -120                                  -118
1k        -140                                  -141
10k      -145                                  -160
100k      -145                                  -161

so not bad apart from the raised floor.  (I am assuming that an ideal 5x
multiplication on the 16.384-MHz version of the VFOV405 would yield a
similar comparison to an 80-MHz ABLNO.)

Using this handy tool: https://rf-tools.com/jitter/  it looks like 0.5
ps should be achievable as long as the floor is kept to -145 dBc/Hz
(integrating 10 Hz to 10 MHz).  The multiplier scheme will need to
contribute very little residual noise far out.  No idea how easy/hard
that will be. More than 0.5 ps jitter will start to degrade the ADC
performance significantly.

Regards,
Mark

On Mon, 20 Jan 2020 14:44:01 -0500
Bob kb8tq kb8tq@n1k.org wrote:

No, these are from Ebay.  A guy in Texas has been salvaging them from
(I assume) telecom equipment:
https://www.ebay.com/itm/CTS-16-384MHz-OCXO-3-3V-Oven-Controlled-VFControl-50ppb-120mW-VFOV405-TCEDH/113877523761?hash=item1a83a11d31:g:3JQAAOSwxN5WXv4q

Obviously all of the caveats about used OCXOs apply, but at least they
weren't melted off of scrap PCBs by kids in China.  This is a hobby
project so I don't plan to build more than half a dozen of my
design-in-progress.  Assuming it happens at all ;)

Regards,
Mark

On 1/20/20 11:44 AM, Bob kb8tq wrote:

Been there, done that.  I have a few extra 100 MHz tiny Vectron EX-421
OCXOs at work because I had to order more than the 3 I needed. I need to
find a project at work to use them.

These are 100MHz units, ran about $262 each (in qty 6) (I'm going to
guess that Vectron has a minimum order of $1500 or something like that)

The PN performance is better than either of the other two, but it's also
not a VCXO. It's probably "representative" of the performance that's
achievable in a small package at low power, though.

FWIW, they seem to work fine in space, although they're not space
qualified - over 6 months or so, I didn't see any particular changes in
frequency compared to GPS or a CSAC that wouldn't just be aging.

Hi

If indeed -145 is “good enough” then you have moved out of the “good phase noise”
region into fairly generic sort of specs. A “couple of dollar” oscillator will give you -145
sort of noise floors.

The value of 12 db at 10 Hz offset is going to be pretty limited unless the application
is very unusual.

Bob

Hi

Hmmm … wonder who talked you into that silliness …. :) :) :)

Bob

On Mon, 20 Jan 2020 15:25:00 -0500
Bob kb8tq kb8tq@n1k.org wrote:

True enough, but remember that my motivation for using the OCXO in the
first place was to combine the required phase-noise spec with
OCXO-class frequency stability (this is for narrowband coherent
modulation schemes on the shortwave bands where short-term stability of
~ 10^-10 is nice to have).  The alternative is what Attila said,
VCXO phase locked to an OCXO.  The advantage of doing it this way is
that I [potentially] reduce complexity, board space, and power.

Hypothetically, sure, any old 80-MHz OCXO with "generic" phase-noise
performance would suffice.  But hobbyists can't just pick up the phone
and order something like that; we're limited to surplus/used stock,
where 80-ish MHz is unusual.  And of course most surplus/used OCXOs
would require high voltage (5V or above), high power (half a watt or
more), or both.

Sorry, I didn't plan to expound on my design rationale at such length,
but you seemed curious :)

Regards,
Mark

Hi

I think you will find that some fairly generic oscillators will hit the “more or
less 1x10^-10” sort of spec needed for HF com work. A good OCXO will get
you into the 1x10^-12 range. The limit generally is the “floor” imposed by
propagation variance at HF.

Bob

On Mon, 20 Jan 2020 12:50:09 -0800
Mark Haun mark@hau.nz wrote:

For an SDR application, the ABLNO allone would be the best option, IMHO.
It's low power and low noise. Even for narrowband SW applications.
If you look at the data, you see that the cross-over between the
ABLNO is lower noise to the OCXO is lower noise is around 100Hz.
Unless you are operating at much lower than 100baud, the ABLNO
is going to be enough. If you are using something like AFSK31/PSK31
it's probably borderline which one is better and I would go with
the ABLNO only for simpler construction and easier sourcing.

If you are thinking about trpoposcatter, EME or similar things
with really low baud rates, then I would go for the VCXO+PLL
approach for one simple reason: Flexibility. With a PLL you
have a choice what kind of reference you want to use.
E.g. converting the system to use a MV86 would be just a different
footprint and different register settings for the PLL.

And then there ia third way, which is IMHO even better:
Your application is an SDR system, i.e. you already need some
signal processing for the system to work. Why not extend this
to use it for the reference as well? Add another ADC and feed
the reference signal to that, then track the phase/frequency
relation between the sampling clock and the reference and
compensate any drift in the signal path. This way you get to
disable the reference if it is not needed and save a lot of power
and at the same time are able to use references with any frequency
and can change the "loop frequency" freely without the need to
worry about PLL stability or tempco of filters in the multiplier
version.

		Attila Kinali

--
<JaberWorky> The bad part of Zurich is where the degenerates
throw DARK chocolate at you.

On 1/20/20 12:50 PM, Mark Haun wrote:

Learning about design rationale is what this list is all about.

As Bob and others have pointed out over the years, oscillator
manufacturers will happily give you what ever you specify, for a price.
But it's not unusual to have a low volume application where you're
willing to take what you can get, as long as it meets some other
requirement (cost, delivery time).  The problem is that it's hard to
convey all the trades in a requirements or spec document. "Sure, I'm
happy to have high far out noise, but I care about noise between
10-1000 Hz" or "I don't care about absolute frequency stability over
temperature or long term, because I'm putting it in an oven and I'm
going to be able to discipline/measure it, but I want really good close
in noise"

The amateur radio person wanting to multiply their reference up to 10
GHz for narrow band CW is a fine example - They probably have way to
measure frequency, so absolute stability isn't all that important. And
they want low power (because you're sitting on some mountain top with
batteries).  And, there's only a few hundred people in the entire world
who would conceivably be interested in it, and maybe 3 who would try,
and they all want to spend less than $100.

Vectron, Abracon, etc. do not have a business case that contemplates
this idiosyncratic market (nor should they).

But it is useful to know what the "care-abouts" are, because often,
there is lore (that cannot be used as a spec) about stuff that might work.

For my space OCXO need, I started by asking manufacturers if they could
make me a small OCXO with the heater disconnected - so I didn't have to
spend heater power or have a 15V power supply. I wound up with a OCXO
that did have a heater, but the heater power is negligible.  And, as a
side effect, it actually gives me visibility into the internal state of
the device, because by knowing just bus current vs time, I can tell
approximately what temperature things were at when it was turned on.

On 1/20/20 1:13 PM, Bob kb8tq wrote:

And the source's phase noise. There are relatively few "spectrally pure"
transmitters in the HF band that are sufficiently clean that you can
measure the ionospheric effects. WWV/H, ARRL FMTs, ionosondes (maybe),
and a few other things.

For what it's worth, the decorrelation time for ionosphere is about 3
seconds. That is, the state of the ionosphere on any given path is
almost entirely uncorrelated to the state 3 seconds earlier. So AVAR at
100 seconds isn't worth a whole lot, unless you're measuring the ionosphere.

On 1/20/20 1:57 PM, Attila Kinali wrote:

This ...

This is the way of the future.  The problem is that there are enough
legacy systems out there where you need "control" vs "knowledge"

And, in the SDR world: while theoretically, you can do this in software,
a lot of times the software is either a black box, or incomprehensible
in finite time, or architected in a way that makes it hard, that it's
actually faster and easier to discipline the reference oscillator than
to fix the software.

I say this as someone who makes his living designing, building, and
using SDRs - a Curse on Matt Ettus and USRPs, gnuradio, pothos, etc. and
their ease of use, allowing positive legions of people to produce
software which is horrible, without realizing the implications and
defects within.  They should all be consulting me before engaging in
these ill advised implementations based on textbook descriptions from
Oppenheim and Schaefer, etc.

But yes, the best way to do it is to measure the oscillator and use
that to correct the digitized data, rather than driving the oscillator.
It is challenging, though, to do this in a system where there is a need
for full duplex operation (i.e. the transmitted signal needs to be
adjusted to match the received signal).

Hi

If your “reference” is a 10 MHz OCXO, that may well come down on top / very near something you might want to
receive. Having seen what WWV uses as an exciter … indeed their noise “as transmitted” is pretty darn good.

If the reference is 16.384 …. hmmm …. maybe not so much. I can’t think of much around there worth tuning in to.
Simply feeding the OCXO (at a very low level) into a single ADC might well do the trick. ( yes, you have a number
of things to dig into, it’s not quite the slam dunk I’m making it out to be).

Bob

On Mon, 20 Jan 2020 17:31:51 -0500
Bob kb8tq kb8tq@n1k.org wrote:

I was about to say that adding a second ADC channel is really expensive
(like $50 between AD9266 and AD9269), but I really like this idea...
just couple a reference oscillator into the main signal path at an
appropriate level, then use a parallel receive path in the FPGA
to trim the NCOs for the known beacon frequency.

Unfortunately I suspect the added digital power consumption in the FPGA
would be greater than the analog power for a PLL solution.  As much as
it pains me to say that as a DSP guy ;)  I need to think about this
some more, though.

Thanks for the ideas,
Mark

Am 20.01.20 um 22:57 schrieb Attila Kinali:

For a back burner project, motorcycle based portable 432 MHz EME,
(i.e. collecting squares with a friend of mine who has a huge antenna),
I decided to use one of these

< https://www.digikey.de/de/product-highlight/e/ecs/ecoc-2522-smd-ocxo   >

and call it a day.

432 - (4*100) = 32 MHz = somewhere in the middle of the Red Pitaya passband.
And the Red Pitaya could also run on the 100 MHz. There happen to exist nice
SAW-Filters for both 400 and 432 MHz. No tuning.

There is no Baud rate on EME, just a 600 Hz side tone. :-)     Or WSJE.

regards, Gerhard, DK4XP

On Mon, 20 Jan 2020 15:40:08 -0800
Mark Haun mark@hau.nz wrote:

You don't need a high performance ADC for the reference as you are dealing
with a narrow band signal of known frequency. Even a 10bit or 8bit ADC
would be good enough. You can even go and sample at half frequency
and save both money and power. This works because the required bandwidth
of the signal to track properly is low, somewhere in the order of 1-10kHz
should be enough. Thus working with just a few bits on the ADC and then
decimating you get lots of bits. E.g. going from 40MHz to 40kHz results
in approximately 9bits more. Starting from a 8bit ADC this gives something
around 15bits (probably more like 12-14bits, not accounting for ADC and
sampling noise and numerical precision), which is already good enough
to track at a rate of 100-500Hz.

If you choose a different frequency for the sampling clock, that is
"odd", let's say 155.52MHz/2=77.76MHz, you can sample even further
down (e.g. at 7.776MHz) and get to lower cost and lower power ADCs.

There is one key parameter for this ADC that you should not skimp on, though.
It's apperture jitter, as this directly translates into tracking noise of
the reference.

Hmm... My gut feeling would say that the ADC+tracking approach should
be lower power... But I have not done the calculation, so I might be wrong.
But yes, there are several design choices and trade-offs that need to be
balanced, that directly affect cost and power consumption.

			Attila Kinali

--
<JaberWorky> The bad part of Zurich is where the degenerates
throw DARK chocolate at you.

On 1/20/20 3:40 PM, Mark Haun wrote:

Many (big) FPGAs these days have power consumption dominated by the
leakage current of all the gates. Even going back as far as the Virtex
4, the dependence of power on clock rate and number of gates toggling is
pretty small.

I've not checked something like a Zynq.

On Mon, 20 Jan 2020 16:34:08 -0800
jimlux jimlux@earthlink.net wrote:

This is why I'm targeting a small-ish Spartan 7, probably XC7S25.
Datasheet quiescent current on all supplies is on the order of 70 mW.
Pretty impressive when compared with only a couple of generations ago.
And even this small FPGA gives you 80 DSP blocks and 1.6 Mbits of block
RAM.

Mark

On Tue, 21 Jan 2020 01:15:45 +0100
Attila Kinali attila@kinali.ch wrote:

I just spend a few minutes looking at ADCs and found the LTC2256-12
and its faster sister LTC2257-12. They go for ~15USD at quantity 1.
Both have 170fs RMS apperture jitter and do 25Msps and 40Msps respectively.
3dB BW is 800MHz, so more then good enough to even use the 100MHz output
of an hydrogen maser, if you want a really good reference ;-)

Power consumption at max sample rate are 34mW and 47mW respectively.
That's slightly more than a PLL would use (~20mW, plus maybe another
5mW to 10mW for the opamps in the loopfilter). Power consumption goes
down a bit with decreasing sample rate, but not as much as one would
hope for.

			Attila Kinali

--
It is upon moral qualities that a society is ultimately founded. All
the prosperity and technological sophistication in the world is of no
use without that foundation.
-- Miss Matheson, The Diamond Age, Neal Stephenson

Dear Gerhard,

Prologix controllers pass data as is from the instrument to PC. It does not add any termination characters.
++eos command controls how termination is handled for data going the other way -- from PC to instrument.
Please consult instrument manual about how it terminates output.

Hope that helps.

Regards,
Abdul

-----Original Message-----
From: time-nuts [mailto:time-nuts-bounces@lists.febo.com] On Behalf Of Gerhard Hoffmann
Sent: Sunday, January 19, 2020 3:04 PM
To: time-nuts@lists.febo.com
Subject: Re: [time-nuts] Odd-order multiplication of CMOS-output OCXO

Am 19.01.20 um 22:20 schrieb Magnus Danielson:

It's not that the high Q circuit generates noise, it's more

that the phase runs away when the resonant frequency runs away.

For a minimum phase network, you have +- 45° at the -3 dB points.

Ha, that hurts! Sheer mockery! I have spent the entire weekend

trying to control my 89441A FFT analyzer from Linux via a

Prologix USB-to-IEEE488 dongle. Setting /dev/ttyUSB0 to raw

and getting rid of the buffering was easy. Telling if that !#&%§!!

Prologix thing terminates the strings to the computer with LF

or CRLF seems impossible to predict, in spite of a command to

set this. And there is no way to measure anything on that virtual

tty port to watch the traffic. Use of tees activates buffering, no

way around.

Typical Heisenbug. Observing it affects the outcome.

The idea was just to measure 1/f noise on my AF and RF transistors

in a circuit inspired by that in Art Of Electronics V3.

Good book. Must have.

I have cut out the output amplifier circuit of my OCXO support

board and removed the doubler option and the notch filter. It provides

22 dBm after a MV89A, enough for two ranks of power dividers in front

of the Timepod.  Transformers are still sub-optimum, esp. at the low end

and on the output side, but I wanted to avoid winding them myself.

DC emitter degeneration is 50 Ohm to fight 1/f, less than that above a

few 100 KHz as fits the gain. Push-pull common base.

A 10 MHz MV89A is internally 5 MHz, and you can see that in the spectrum.

External notch definitely required.

regards, Gerhard

Hi Attila,

On Tue, 21 Jan 2020 15:08:16 +0100
Attila Kinali attila@kinali.ch wrote:

I hope you will indulge one more newbie question on the analog PLL
option... as I have approximately zero experience designing them.

What are the adverse consequences of using large divisors in the loop,
as would be required for my odd OCXO frequency?  E.g. on paper, it would
seem that I could use 80 MHz / 625 = 16.384 MHz / 128 = 128 kHz PFD
frequency.  How would this differ from a more "normal" ref clock
frequency of 10 or 16 MHz with smaller divisors?

Thanks,
Mark

Hi

The dividers and the phase detectors have noise floors. As you go to higher
divide ratios these get in the way of “preserving” the reference phase noise.

Bob

On 1/21/20 10:41 AM, Mark Haun wrote:

You have potential spurs at the PFD frequency and multiples of it, so it
kind of depends on what bandwidths you have in things like the loop
filter and downstream in the output path.  A higher comparison frequency
puts the first spur farther out.

Hi All,

I am not an expert here, but I can say with some certainty that a divided
clock works well.  I have a system with a 4GSPS RF ADC and a aux ADC which
runs at 1/64th the RF ADC.  The whole clock chain is a 10MHz ext ref -> a
LMX2581 synth -> RF ADC -> RF ADC DCO -> nb4l52 clk in with a D coming from
an FPGA as the AUX ADC clock.  The AUX ADC is able to time stamp a 1pps to
a 1sigma of less than 15ps (difference between the 1PPS into the AUX ADC
and a copy into the RF channel).

The point being what is wrong with a good 80MHz ocxo or tcxo for the main
ADC and and a divided by 4 or 5 to an aux ADC?  And, I have made an HF
transceiver with a ltc2195 and a simple 125MHz ECL oscillator, and some
250MSPS Analog devices DAC which managed QAM256.

It seems like this is being a little over thought.

Run your main ADC at 80MSPS, and free run your oscillator, and present a
reference either through a aux ADC, or as a secondary clock to an FPGA.  No
need to multiply.

-- mike

On Tue, Jan 21, 2020 at 8:25 PM jimlux jimlux@earthlink.net wrote:

Hi Mark,

On 2020-01-21 19:41, Mark Haun wrote:

From my experience, such factors and rate of phase comparator is
relatively easy to work with and get to work reasonably well for most
purposes. I recommend you to use a PI-loop.

For a step-up you want to keep the PLL bandwidth fairly large, and that
helps making it easy.

I've been tempted to do a bunch of such loops in various kinds of
equipment to solve issues. I should to more of them. One should have a
nice little lock-up board to just apply.

Cheers,
Magnus

On Wed, 22 Jan 2020 00:30:12 +0100
Magnus Danielson magnus@rubidium.se wrote:

Why is this?  In my primitive understanding, the loop bandwidth sets the
point where the phase-noise characteristics of the reference and the
VCO are "glued together."  Because my VCXO has good phase noise, and
lacks only stability (say 0.1 to 1 sec and longer), I would have
thought I would want a small bandwidth---basically I want to preserve
the phase-noise characteristics but keep it from drifting.

I know ADI has a nice tool for PLL design; I'll check it out.

Regards,
Mark

On 1/21/20 3:30 PM, Magnus Danielson wrote:

One might also look at a fractional-N PLL - just a bit more flexibility
in where the spurs go.

Hi

Pretty much everybody who wants to sell you a PLL chip also has free
simulation software to give you some idea what that chip does. None of
them are perfect. They all take a bit of time to get used to. Some of them
(Analog Devices stuff) will deal with noise. You can get a pretty good feel
for the noise floor and spur issues involved.

Bob

Hi,

On 2020-01-22 01:05, Mark Haun wrote:

With higher bandwidth, it follows the reference tighter. Consider that
the bandwidth of the PLL is related to the time-constant for it to react
to both the reference and the steered oscillator, and it will low-pass
filter the reference and high-pass filter the steered oscillator, and
higher bandwidth thus suppress more variations of the steered
oscillator, relaxing thermal issues for instance.

If you have a loop filter being a low-pass filter rather than PI-loop,
then you also get better lock-range, quicker lock-in and smaller
phase-errors due to thermal effects or oscillator differences. For a
PI-loop you essentially remove it from being an issue anyway and you can
focus your bandwidth on phase-noise considerations, but the high-pass
vs. low-pass balance remains an issue for compromise.

For step-up PLLs, you typically wants a high bandwidth to keep tight
phase with the reference, but for a clean-up PLL you want a low
bandwidth to filter out as much noise from the reference.

As you compare the phase-noise of the reference and steered oscillator,
as compared on the same frequency, the optimum bandwidth is usually
where they cross each other. This assumes that you actually considered
all the variations.

Cheers,
Magnus

On 1/21/20 4:19 PM, Bob kb8tq wrote:

Dean Banerjee's book is also useful. You used to be able to download it
from National Semiconductor, but now they're part of TI.

You can buy the 5th edition on paper, but here it is as a pdf

http://www.ti.com/lit/ml/snaa106c/snaa106c.pdf

you can read it, but not print it.

Hi

…….. and assuming the noise floor of the dividers and the noise floor of the phase
detector is anywhere near good enough to be useful compared to your super duper
low noise oscillators ….. With good OCXO’s and VCXO’s this may indeed be a gotcha.
With a simple VCO and TCXO from “low bidder industries” , maybe not so much.

( in genera with good oscillators l, this forces you to a narrower loop than you might
have anticipated ….)

Again, playing with simulation software  just might be a good idea. For the brave, you
can buy various books and dig up all sorts of formulas. Those can be dumped into
spread sheets and validated …..

Bob

On Wed, 22 Jan 2020 00:30:12 +0100
Magnus Danielson magnus@rubidium.se wrote:

FWIW, here (attached) is the best result I obtained from ADISimPLL
for locking an 80-MHz VCXO (Abracon ABLNO) to a 16.384-MHz OCXO
reference.  This uses the ADF4002 with a loop bandwidth of only 40 Hz;
larger than that and it says the ADF4002 noise is affecting the result.
Also, the tool is quite limited in how you specify phase noise of the
reference and VCO, so I couldn't quite get the reference noise to match
the datasheet plot---it should be better than what is shown.  The VCXO
noise is pretty close though.

Mark

Jim wrote:

The 4th ed. is available at
http://www.ko4bb.com/getsimple/index.php?id=manuals

It is a  fully functional PDF file.  File name is "PLL Performance
Simulation Design 4th 2006 BANNERJEE.pdf" [NOTE misspelling of author's
name]

Best regards,

Charles

And what, precisely, are “The X Chapters”?

DaveD

Hi,

On 2020-01-22 19:02, Charles Steinmetz wrote:

Mine arrived this afternoon. Thanks for the recommendation.

Now, I've not had much time to look at it, but for sure, it seems to be
more of the same in a good way.

One little sub-chapter is about the spikes from rectifying diodes. It is
really nothing new, it's been known in the field for a long time, but it
is good to see it treated here.

The field of differential amplifiers is covered more deeply for instance.

Looks interesting.

If I had time I would read more out of v3 and x, as in all, but I cannot
dedicate that much time to it.

Cheers,
Magnus

Hi, Abdul!

Am 21.01.20 um 19:10 schrieb Prologix:

But then there is the ++eot command just to set up this.

I also could not see what the timeout does. When I try to read a
character and
none is available it still hangs forever, even with the timeout set to 2
seconds.

We should take that offline probably.

In the meantime, the LAN connection to the FFT analyzer works again.
Ansi C requires some re-synchronisation when switching the direction of
the data
flow in a TCP/IP connection or you may get old messages a second time.
An otherwise empty fseek() is enough, per side effect.
A year ago, the connection to the analyzer was solid, then it would hang
now & then
and in retrospect, since I have the current V5 Linux kernel it is unusable.
The fseek() has healed that.

There is still the minor? problem, that from low to high frequencies,
many new decades
start with elevated noise, but I correct for the increased noise
bandwidth. Maybe discrete
spurii are then over-represented? I'm unsure how to handle that. When I
add a carrier
from a signal generator for CAL reasons, that carrier level should not
be changed by noise BW
correction, assuming that all of the carrier power hits the same bin?

The amplitude of the carrier in the picture has been corrected for 5
decades = -50 dB,
and that's obviously wrong, the 3325B is not that bad. When I do a
narrowband sweep, it
looks OK on the FFT analyzer screen.

Even when I go through the spectrum and decide that this or that is a
carrier and it should
not be downscaled, how do I handle its sidebands? There is no pure black
and white.

Cheers, Gerhard

Hi Gerhard,

On 2020-01-24 00:48, Gerhard Hoffmann wrote:

I fail to see that this is Ansi-C related. There seems to be a few
things missing in the discussion here.

You should never assume that all the carrier power hits the same bin.
This is known to lead to incorrect measurements, and under-estimating
the carrier power. I've made the same comment in the P1139 working
group. The full power of the carrier includes it sidebands, it's the
power which you would measure wide-band into a power-meter.
Underestimating the carrier power leads to increase the sideband powers,
and it can even lead to non-sensible measures as positive dBc values
that can be had when deep PM suppresses carrier and eventually nulls it
(Bessel polynomial - B0).

It has been described way to hand-wavey and confusion becomes a consequence.

I have proposed that carrier power estimation should ensure 3-sigma
(99,7%) of power is caught, which seems reasonable for many purposes.
Exactly how that is done and achieved is then left as an exercise to the
implementer, but I think it is a good rule of thumb to start from.

Cheers,
Magnus

On 1/23/20 4:20 PM, Magnus Danielson wrote:

Not only that, but don't forget errors due to the window of your FFT -
if your frequency isn't dead center in a bin, the power is distributed
among multiple bins.  And if it is dead center in a bin, there's still
the window effects.

There's a whole literature on accurate power measurements using FFTs,
along with a lot of exotic windows (i.e. not a simple raised cosine or
something like that) that have very good sidelobe performance. For run
of the mill work, I use a Blackman-Harris window, mostly because it's in
most libraries and has sidelobes more than 80 dB down (vs rectangular at
13 dB down, or Hamming at -42 dB). Hamming windows are fine for 1% (8
bit) systems.

Not all spectrum analyzers which display total power or carrier vs
sidebands or spurious levels, do a good job of automatically computing
this kind of thing. You really need to check with some known signals (or
carefully read the spectrum analyzer ap-notes).  The worst are so
called spectrum analyzer apps and blocks in things like gnuradio, or
"software spectrum analyzers" implemented on one of the inexpensive SDR
platforms.

For what it's worth, there are also power meters (usually combined
with a counter) which have a narrow band filter that tracks the input
signal. The Agilent 53152, for instance, might give you a different
power reading than an old school power meter like a 437 with a 8480
series power sensor.

Granted, a lot of this is worrying about millibels (0.01 dB), but as
Magnus points out, you can come up with unphysical derived measurements
like spurious signals > total power.

Here's a 200 page catalog of window functions from Sandia:
https://prod-ng.sandia.gov/techlib-noauth/access-control.cgi/2017/174042.pdf

SANDIA REPORT SAND2017-4042

Printed April 2017
Catalog of Window Taper Functions for Sidelobe Control
Armin W. Doerry

It has some excellent explanatory information and examples at the
beginning and data on dozens of windows, with plots.

It will save you the trouble of getting Fred Harris's IEEE Proceedings
paper, and the later ones by others like Nuttall.  The Harris paper is
useful, though.
F. J. Harris, "On the use of windows for harmonic analysis with the
discrete Fourier transform," in Proceedings of the IEEE, vol. 66, no. 1,
pp. 51-83, Jan. 1978.
doi: 10.1109/PROC.1978.10837
http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1455106&isnumber=31261

there are copies around at places like the MIT website. It's well up
there on the "cited count" well over 8000.  I could only dream of
writing such a paper.

I warn you though - You can go down a rabbit hole on this - there are
people who have tried to reverse engineer the windows used on equipment
like HP/Agilent/Keysight analyzers, or who have developed windows with
some peculiarly useful property for some specific signal (low sidelobes
around known spurs, etc.)

However, this is time-nuts, not window-nuts.

Yes, that spill-over to neighbor bins is a known thing; when I wrote
software

for mixed signal wafer testers we sometimes used no windows at all and

instead made sure that all frequencies involved were proper submultiples

of the sample rate. In my current situation I'm limited to what the 89441A

has to offer, and that is not too much. IIRC the manual proposes flat top

for sines and Hanning for noise. While there is no such thing as a Hanning

window. That Guy was Justus von Hann, from Austria.

Carriers are also not of prime interest at the moment; I'm more focused

on the noise itself. Maybe 1/f of oscillator transistors or the noise of

GaN fets in a pV/rtHz chopper amplifier where the GaN have some appeal

for low charge injection. When I used my URV-35 with the Z51 thermal

head to measure the noise, the result would be dominated by the 1/f,

even though the Z51 collects everything to 18 GHz.

And when I measure phase noise, the carrier has already been

carefully and lovingly removed.

With all that TCP/IP and GPIB programming and C library feature

flavor macros I feel already quite deep in the wrong rabbit hole.

My test carrier is not off by milliBels but by 50 dB and correcting that

won't probably work without some lying where the carrier hits the noise
floor.

Cheers,

Gerhard, DK4XP

Am 24.01.20 um 01:59 schrieb jimlux:

.....