Discussion and technical support related to USRP, UHD, RFNoC
View all threadsHi,
I am looking to do some channelization on the B200, how much space is
available on its FPGA after the default image is loaded?
I am new to FPGAs, and wondering what the reasonable expectation should be
If there is not really room for any of that on the B200, would it make
sense to use another USRP (and if so which), or perhaps something like NI's
myRIO?
Thanks!
T.
If you want to do FPGA development on the B-series, the B210 might be a
better choice, as it has the functionality and capabilities as the B200,
but with a larger FPGA. You will need Xilinx ISE, System Edition, version
14.7 or later to build FPGA images. The free Xilinx ISE WebPack Edition
will not work.
--Neel
On Wed, Jan 14, 2015 at 12:49 PM, Tal Achituv via USRP-users <
usrp-users@lists.ettus.com> wrote:
Hi,
I am looking to do some channelization on the B200, how much space is
available on its FPGA after the default image is loaded?
I am new to FPGAs, and wondering what the reasonable expectation should be
If there is not really room for any of that on the B200, would it make
sense to use another USRP (and if so which), or perhaps something like NI's
myRIO?
Thanks!
T.
USRP-users mailing list
USRP-users@lists.ettus.com
http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
Hi Tal,
I can't estimate the utilization of a NBFM channel off the top of my head
but here is the utilization for the default B200 and B210 images. If your
channelizer does not need too much block RAM and just utilizes logic blocks
and DSPs then you could possibly fit something in the B210.
Slice Logic Utilization:
Number of Slice Registers: 12007 out of 93296 12%
Number of Slice LUTs: 17149 out of 46648 36%
Number used as Logic: 14889 out of 46648 31%
Number used as Memory: 2260 out of 11072 20%
Number used as RAM: 336
Number used as SRL: 1924
Slice Logic Distribution:
Number of LUT Flip Flop pairs used: 20332
Number with an unused Flip Flop: 8325 out of 20332 40%
Number with an unused LUT: 3183 out of 20332 15%
Number of fully used LUT-FF pairs: 8824 out of 20332 43%
Number of unique control sets: 301
IO Utilization:
Number of IOs: 172
Number of bonded IOBs: 156 out of 280 55%
IOB Flip Flops/Latches: 138
Specific Feature Utilization:
Number of Block RAM/FIFO: 144 out of 172 83%
Number using Block RAM only: 144
Number of BUFG/BUFGCTRLs: 5 out of 16 31%
Number of DSP48A1s: 16 out of 132 12%
Slice Logic Utilization:
Number of Slice Registers: 21608 out of 184304 11%
Number of Slice LUTs: 30782 out of 92152 33%
Number used as Logic: 27069 out of 92152 29%
Number used as Memory: 3713 out of 21680 17%
Number used as RAM: 480
Number used as SRL: 3233
Slice Logic Distribution:
Number of LUT Flip Flop pairs used: 36833
Number with an unused Flip Flop: 15225 out of 36833 41%
Number with an unused LUT: 6051 out of 36833 16%
Number of fully used LUT-FF pairs: 15557 out of 36833 42%
Number of unique control sets: 461
IO Utilization:
Number of IOs: 172
Number of bonded IOBs: 156 out of 338 46%
IOB Flip Flops/Latches: 154
Specific Feature Utilization:
Number of Block RAM/FIFO: 186 out of 268 69%
Number using Block RAM only: 186
Number of BUFG/BUFGCTRLs: 5 out of 16 31%
Number of DSP48A1s: 32 out of 180 17%
Ashish Chaudhari | Senior Software Engineer | High Frequency Measurements
On Wed, Jan 14, 2015 at 12:49 PM, Tal Achituv via USRP-users <
usrp-users@lists.ettus.com> wrote:
Hi,
I am looking to do some channelization on the B200, how much space is
available on its FPGA after the default image is loaded?
I am new to FPGAs, and wondering what the reasonable expectation should be
If there is not really room for any of that on the B200, would it make
sense to use another USRP (and if so which), or perhaps something like NI's
myRIO?
Thanks!
T.
USRP-users mailing list
USRP-users@lists.ettus.com
http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com