I took over master bedroom for my lab, and I have a gate for dog entry prevention. All cables are over-head. I need protection from 2 legged and 4 legged variety.
(Mr.) Taka Kamiya
KB4EMF / ex JF2DKG
On Monday, February 24, 2020, 10:47:20 AM EST, Bob kb8tq via time-nuts <time-nuts@lists.febo.com> wrote:
Hi
…… looking at the data this morning. It appears that in my case somebody
(I’m blaming the dog) must have bumped the setup. There is a very obvious
set of steps in the phase data. The overnight run has no similar steps. Sometimes
getting everything away from the test is a good thing …..
Bob
On Feb 23, 2020, at 7:51 PM, Bob kb8tq kb8tq@n1k.org wrote:
Hi
Ok, but thats “high pass in the RF section”. You really do not have an audio high pass
filter the way you would in a more typical DMTD.
If it’s any comfort, I’m sitting here looking at a very different box. It also has “wobbles”
as you get into parts in 10^-16. That might change a bit if the draft coming through the
window was a bit less.
Bob
On Feb 23, 2020, at 6:12 PM, Jan-Derk Bakker <jdbakker@gmail.com mailto:jdbakker@gmail.com> wrote:
Dear Bob,
The capacitors are 47n NP0/C0G types (Kemet C0805C473K3GAC7800), picked for low tempco (and low DF and other non-ideal behavior). I've not spotted any hysteresis artefacts in these in previous designs, but I haven't measured their performance in this circuit.
Forgot to mention in the previous message: the baluns are transformers (M/A-COM MABAES0060), so the only DC the ADC should see is its own input offset (plus offset current across the 25R input filter resistors). Full schematic is here ( http://www.lartmaker.nl/time-nuts/DMTD_rev0.99.pdf http://www.lartmaker.nl/time-nuts/DMTD_rev0.99.pdf ; needs cleanup, but all connections are there).
JDB.
On Sun, Feb 23, 2020 at 10:13 PM Bob kb8tq <kb8tq@n1k.org mailto:kb8tq@n1k.org> wrote:
Hi
What does the temperature coefficient of your “hardware HPF” filter caps look like?
Are they a type that has significant hysteresis?
Bob
On Feb 23, 2020, at 3:05 PM, Jan-Derk Bakker via time-nuts <time-nuts@lists.febo.com mailto:time-nuts@lists.febo.com> wrote:
Dear Attila,
Thanks for the heads up.
I am currently using a HPF both in hardware (capacitive coupling into the
balun driving the ADC inputs) and in software before the ZCD. This should
counteract the first-order effects of this offset, although second-order
effects (converter nonlinearity et al) will of course still be an issue.
The plots you've quoted include (different kinds of) DC offset correction
for all but the "unfiltered" data; getting an efficient DC offset
correction working in real time on this 8-bit platform was indeed one of
the main challenges of the software-only approach.
The FPGA daughterboard is currently in production at Eurocircuits; I hope
to have time to work on those the coming month. I'll also try to book some
time in our climate chamber. (I've had one of our GPSDO-designs running in
our general labs since before Christmas; surrounding it with bottles of
water works well enough to low pass filter temperature swings, but I still
see 6 degrees C swings overnight as out HVAC only runs during business
hours.)
To be continued,
JDB.
On Sun, Feb 23, 2020 at 8:11 PM Attila Kinali via time-nuts <
time-nuts@lists.febo.com mailto:time-nuts@lists.febo.com> wrote:
Good evening!
I'm going through some old stuff...
On Wed, 27 Nov 2019 00:29:19 +0100
Jan-Derk Bakker <jdbakker@gmail.com mailto:jdbakker@gmail.com> wrote:
This has yielded a combined "simple" signal
processing path of a differentiator, a double comb filter and the offset
estimator, which is getting very close in performance to the "ideal" band
pass filter (OADEV of 3.77e-13@tau=1s versus 3.25e-13@tau=1s for the
BPF;
full plot:
http://www.lartmaker.nl/time-nuts/DMTD%20self-noise%20OADEV%20with%20PLL%20and%20various%20filters.pdf http://www.lartmaker.nl/time-nuts/DMTD%20self-noise%20OADEV%20with%20PLL%20and%20various%20filters.pdf
for this 600000-second recording:
http://www.lartmaker.nl/time-nuts/600ksec%20run%20with%20PLL,%2010811%20through%20splitter.png http://www.lartmaker.nl/time-nuts/600ksec%20run%20with%20PLL,%2010811%20through%20splitter.png
. OADEV past ~1000sec is severely compromised by the fact that the
measurement setup is in my home lab which sees temperature swings of up
to
20 degrees C and which does get bumped from time to time. Longer runs in
a
more controlled setting forthcoming).
I can offer an explanation for the large effect of the zero correction seen
here. The LTC2140 is specified to have a +/-10µV/°C drift (at 1Vpp
setting).
Converted into phase error due to zero crossing shift, this turns into
a phase shift of +/-1ps/°C @ 10MHz. Note, the shift is given as +/- and
per channel, which means, it could very well be that the channels are
not matched in their temperature characteristics and thus the total phase
shift could be +/-2ps/°C ... though total shift being closer to 0.5ps/°C is
more likely.
Summa sumarum: DC offset correction is important if a zero crossing
detector is used.
Attila Kinali
--
<JaberWorky> The bad part of Zurich is where the degenerates
throw DARK chocolate at you.
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I woke up this morning, check my HP105B, it's absolutely going nuts. Heater temp down, frequency ALL OVER the place. No output in any of the ports. Sigh..... eBay strikes again!
(Mr.) Taka Kamiya
KB4EMF / ex JF2DKG
On Sunday, February 23, 2020, 7:52:02 PM EST, Bob kb8tq via time-nuts <time-nuts@lists.febo.com> wrote:
Hi
Ok, but thats “high pass in the RF section”. You really do not have an audio high pass
filter the way you would in a more typical DMTD.
If it’s any comfort, I’m sitting here looking at a very different box. It also has “wobbles”
as you get into parts in 10^-16. That might change a bit if the draft coming through the
window was a bit less.
Bob
On Feb 23, 2020, at 6:12 PM, Jan-Derk Bakker jdbakker@gmail.com wrote:
Dear Bob,
The capacitors are 47n NP0/C0G types (Kemet C0805C473K3GAC7800), picked for low tempco (and low DF and other non-ideal behavior). I've not spotted any hysteresis artefacts in these in previous designs, but I haven't measured their performance in this circuit.
Forgot to mention in the previous message: the baluns are transformers (M/A-COM MABAES0060), so the only DC the ADC should see is its own input offset (plus offset current across the 25R input filter resistors). Full schematic is here ( http://www.lartmaker.nl/time-nuts/DMTD_rev0.99.pdf http://www.lartmaker.nl/time-nuts/DMTD_rev0.99.pdf ; needs cleanup, but all connections are there).
JDB.
On Sun, Feb 23, 2020 at 10:13 PM Bob kb8tq <kb8tq@n1k.org mailto:kb8tq@n1k.org> wrote:
Hi
What does the temperature coefficient of your “hardware HPF” filter caps look like?
Are they a type that has significant hysteresis?
Bob
On Feb 23, 2020, at 3:05 PM, Jan-Derk Bakker via time-nuts <time-nuts@lists.febo.com mailto:time-nuts@lists.febo.com> wrote:
Dear Attila,
Thanks for the heads up.
I am currently using a HPF both in hardware (capacitive coupling into the
balun driving the ADC inputs) and in software before the ZCD. This should
counteract the first-order effects of this offset, although second-order
effects (converter nonlinearity et al) will of course still be an issue.
The plots you've quoted include (different kinds of) DC offset correction
for all but the "unfiltered" data; getting an efficient DC offset
correction working in real time on this 8-bit platform was indeed one of
the main challenges of the software-only approach.
The FPGA daughterboard is currently in production at Eurocircuits; I hope
to have time to work on those the coming month. I'll also try to book some
time in our climate chamber. (I've had one of our GPSDO-designs running in
our general labs since before Christmas; surrounding it with bottles of
water works well enough to low pass filter temperature swings, but I still
see 6 degrees C swings overnight as out HVAC only runs during business
hours.)
To be continued,
JDB.
On Sun, Feb 23, 2020 at 8:11 PM Attila Kinali via time-nuts <
time-nuts@lists.febo.com mailto:time-nuts@lists.febo.com> wrote:
Good evening!
I'm going through some old stuff...
On Wed, 27 Nov 2019 00:29:19 +0100
Jan-Derk Bakker <jdbakker@gmail.com mailto:jdbakker@gmail.com> wrote:
This has yielded a combined "simple" signal
processing path of a differentiator, a double comb filter and the offset
estimator, which is getting very close in performance to the "ideal" band
pass filter (OADEV of 3.77e-13@tau=1s versus 3.25e-13@tau=1s for the
BPF;
full plot:
http://www.lartmaker.nl/time-nuts/DMTD%20self-noise%20OADEV%20with%20PLL%20and%20various%20filters.pdf http://www.lartmaker.nl/time-nuts/DMTD%20self-noise%20OADEV%20with%20PLL%20and%20various%20filters.pdf
for this 600000-second recording:
http://www.lartmaker.nl/time-nuts/600ksec%20run%20with%20PLL,%2010811%20through%20splitter.png http://www.lartmaker.nl/time-nuts/600ksec%20run%20with%20PLL,%2010811%20through%20splitter.png
. OADEV past ~1000sec is severely compromised by the fact that the
measurement setup is in my home lab which sees temperature swings of up
to
20 degrees C and which does get bumped from time to time. Longer runs in
a
more controlled setting forthcoming).
I can offer an explanation for the large effect of the zero correction seen
here. The LTC2140 is specified to have a +/-10µV/°C drift (at 1Vpp
setting).
Converted into phase error due to zero crossing shift, this turns into
a phase shift of +/-1ps/°C @ 10MHz. Note, the shift is given as +/- and
per channel, which means, it could very well be that the channels are
not matched in their temperature characteristics and thus the total phase
shift could be +/-2ps/°C ... though total shift being closer to 0.5ps/°C is
more likely.
Summa sumarum: DC offset correction is important if a zero crossing
detector is used.
Attila Kinali
--
<JaberWorky> The bad part of Zurich is where the degenerates
throw DARK chocolate at you.
time-nuts mailing list -- time-nuts@lists.febo.com mailto:time-nuts@lists.febo.com
To unsubscribe, go to
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and follow the instructions there.
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Hi
Yup, welcome to the online auction lottery ….. As you may have noted, I’m
struggling a bit with the Phase Station and random (likely my fault) issues.
At the same time, I’m going around in circles about the R&S FPC-COM2. It’s
a pile of money, but it would replace a lot of questionable gear I have sitting
here. Most of what I have was quite literally pulled from / saved from the
dumpster at various points over the last few decades …..
Bob
On Feb 24, 2020, at 12:33 PM, Taka Kamiya via time-nuts time-nuts@lists.febo.com wrote:
I woke up this morning, check my HP105B, it's absolutely going nuts. Heater temp down, frequency ALL OVER the place. No output in any of the ports. Sigh..... eBay strikes again!
(Mr.) Taka Kamiya
KB4EMF / ex JF2DKG
On Sunday, February 23, 2020, 7:52:02 PM EST, Bob kb8tq via time-nuts <time-nuts@lists.febo.com> wrote:
Hi
Ok, but thats “high pass in the RF section”. You really do not have an audio high pass
filter the way you would in a more typical DMTD.
If it’s any comfort, I’m sitting here looking at a very different box. It also has “wobbles”
as you get into parts in 10^-16. That might change a bit if the draft coming through the
window was a bit less.
Bob
On Feb 23, 2020, at 6:12 PM, Jan-Derk Bakker jdbakker@gmail.com wrote:
Dear Bob,
The capacitors are 47n NP0/C0G types (Kemet C0805C473K3GAC7800), picked for low tempco (and low DF and other non-ideal behavior). I've not spotted any hysteresis artefacts in these in previous designs, but I haven't measured their performance in this circuit.
Forgot to mention in the previous message: the baluns are transformers (M/A-COM MABAES0060), so the only DC the ADC should see is its own input offset (plus offset current across the 25R input filter resistors). Full schematic is here ( http://www.lartmaker.nl/time-nuts/DMTD_rev0.99.pdf http://www.lartmaker.nl/time-nuts/DMTD_rev0.99.pdf ; needs cleanup, but all connections are there).
JDB.
On Sun, Feb 23, 2020 at 10:13 PM Bob kb8tq <kb8tq@n1k.org mailto:kb8tq@n1k.org> wrote:
Hi
What does the temperature coefficient of your “hardware HPF” filter caps look like?
Are they a type that has significant hysteresis?
Bob
On Feb 23, 2020, at 3:05 PM, Jan-Derk Bakker via time-nuts <time-nuts@lists.febo.com mailto:time-nuts@lists.febo.com> wrote:
Dear Attila,
Thanks for the heads up.
I am currently using a HPF both in hardware (capacitive coupling into the
balun driving the ADC inputs) and in software before the ZCD. This should
counteract the first-order effects of this offset, although second-order
effects (converter nonlinearity et al) will of course still be an issue.
The plots you've quoted include (different kinds of) DC offset correction
for all but the "unfiltered" data; getting an efficient DC offset
correction working in real time on this 8-bit platform was indeed one of
the main challenges of the software-only approach.
The FPGA daughterboard is currently in production at Eurocircuits; I hope
to have time to work on those the coming month. I'll also try to book some
time in our climate chamber. (I've had one of our GPSDO-designs running in
our general labs since before Christmas; surrounding it with bottles of
water works well enough to low pass filter temperature swings, but I still
see 6 degrees C swings overnight as out HVAC only runs during business
hours.)
To be continued,
JDB.
On Sun, Feb 23, 2020 at 8:11 PM Attila Kinali via time-nuts <
time-nuts@lists.febo.com mailto:time-nuts@lists.febo.com> wrote:
Good evening!
I'm going through some old stuff...
On Wed, 27 Nov 2019 00:29:19 +0100
Jan-Derk Bakker <jdbakker@gmail.com mailto:jdbakker@gmail.com> wrote:
This has yielded a combined "simple" signal
processing path of a differentiator, a double comb filter and the offset
estimator, which is getting very close in performance to the "ideal" band
pass filter (OADEV of 3.77e-13@tau=1s versus 3.25e-13@tau=1s for the
BPF;
full plot:
http://www.lartmaker.nl/time-nuts/DMTD%20self-noise%20OADEV%20with%20PLL%20and%20various%20filters.pdf http://www.lartmaker.nl/time-nuts/DMTD%20self-noise%20OADEV%20with%20PLL%20and%20various%20filters.pdf
for this 600000-second recording:
http://www.lartmaker.nl/time-nuts/600ksec%20run%20with%20PLL,%2010811%20through%20splitter.png http://www.lartmaker.nl/time-nuts/600ksec%20run%20with%20PLL,%2010811%20through%20splitter.png
. OADEV past ~1000sec is severely compromised by the fact that the
measurement setup is in my home lab which sees temperature swings of up
to
20 degrees C and which does get bumped from time to time. Longer runs in
a
more controlled setting forthcoming).
I can offer an explanation for the large effect of the zero correction seen
here. The LTC2140 is specified to have a +/-10µV/°C drift (at 1Vpp
setting).
Converted into phase error due to zero crossing shift, this turns into
a phase shift of +/-1ps/°C @ 10MHz. Note, the shift is given as +/- and
per channel, which means, it could very well be that the channels are
not matched in their temperature characteristics and thus the total phase
shift could be +/-2ps/°C ... though total shift being closer to 0.5ps/°C is
more likely.
Summa sumarum: DC offset correction is important if a zero crossing
detector is used.
Attila Kinali
--
<JaberWorky> The bad part of Zurich is where the degenerates
throw DARK chocolate at you.
time-nuts mailing list -- time-nuts@lists.febo.com mailto:time-nuts@lists.febo.com
To unsubscribe, go to
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and follow the instructions there.
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and follow the instructions there.
It turns out Bobs dumpster was my dumpster by a long path.
I still have the sampling HP54100 1 Ghz scope and it works.
Many other lucky bits to get.
Best regards
Paul
WB8TSL
On Mon, Feb 24, 2020 at 1:43 PM Bob kb8tq via time-nuts <
time-nuts@lists.febo.com> wrote:
Hi
Yup, welcome to the online auction lottery ….. As you may have noted, I’m
struggling a bit with the Phase Station and random (likely my fault)
issues.
At the same time, I’m going around in circles about the R&S FPC-COM2. It’s
a pile of money, but it would replace a lot of questionable gear I have
sitting
here. Most of what I have was quite literally pulled from / saved from the
dumpster at various points over the last few decades …..
Bob
On Feb 24, 2020, at 12:33 PM, Taka Kamiya via time-nuts <
time-nuts@lists.febo.com> wrote:
I woke up this morning, check my HP105B, it's absolutely going nuts.
Heater temp down, frequency ALL OVER the place. No output in any of the
ports. Sigh..... eBay strikes again!
(Mr.) Taka Kamiya
KB4EMF / ex JF2DKG
On Sunday, February 23, 2020, 7:52:02 PM EST, Bob kb8tq via time-nuts
time-nuts@lists.febo.com wrote:
Hi
Ok, but thats “high pass in the RF section”. You really do not have an
audio high pass
filter the way you would in a more typical DMTD.
If it’s any comfort, I’m sitting here looking at a very different box.
It also has “wobbles”
as you get into parts in 10^-16. That might change a bit if the draft
coming through the
wrote:
Dear Bob,
The capacitors are 47n NP0/C0G types (Kemet C0805C473K3GAC7800), picked
for low tempco (and low DF and other non-ideal behavior). I've not spotted
any hysteresis artefacts in these in previous designs, but I haven't
measured their performance in this circuit.
Forgot to mention in the previous message: the baluns are transformers
(M/A-COM MABAES0060), so the only DC the ADC should see is its own input
offset (plus offset current across the 25R input filter resistors). Full
schematic is here ( http://www.lartmaker.nl/time-nuts/DMTD_rev0.99.pdf <
http://www.lartmaker.nl/time-nuts/DMTD_rev0.99.pdf> ; needs cleanup, but
all connections are there).
kb8tq@n1k.org>> wrote:
Hi
What does the temperature coefficient of your “hardware HPF” filter
caps look like?
Are they a type that has significant hysteresis?
Bob
On Feb 23, 2020, at 3:05 PM, Jan-Derk Bakker via time-nuts <
Dear Attila,
Thanks for the heads up.
I am currently using a HPF both in hardware (capacitive coupling into
the
balun driving the ADC inputs) and in software before the ZCD. This
should
counteract the first-order effects of this offset, although
second-order
effects (converter nonlinearity et al) will of course still be an
issue.
The plots you've quoted include (different kinds of) DC offset
correction
for all but the "unfiltered" data; getting an efficient DC offset
correction working in real time on this 8-bit platform was indeed one
of
the main challenges of the software-only approach.
The FPGA daughterboard is currently in production at Eurocircuits; I
hope
to have time to work on those the coming month. I'll also try to book
some
time in our climate chamber. (I've had one of our GPSDO-designs
running in
our general labs since before Christmas; surrounding it with bottles of
water works well enough to low pass filter temperature swings, but I
still
see 6 degrees C swings overnight as out HVAC only runs during business
hours.)
To be continued,
JDB.
On Sun, Feb 23, 2020 at 8:11 PM Attila Kinali via time-nuts <
time-nuts@lists.febo.com mailto:time-nuts@lists.febo.com> wrote:
Good evening!
I'm going through some old stuff...
On Wed, 27 Nov 2019 00:29:19 +0100
Jan-Derk Bakker <jdbakker@gmail.com mailto:jdbakker@gmail.com>
wrote:
This has yielded a combined "simple" signal
processing path of a differentiator, a double comb filter and the
offset
estimator, which is getting very close in performance to the "ideal"
band
pass filter (OADEV of 3.77e-13@tau=1s versus 3.25e-13@tau=1s for the
BPF;
full plot:
http://www.lartmaker.nl/time-nuts/DMTD%20self-noise%20OADEV%20with%20PLL%20and%20various%20filters.pdf
<
http://www.lartmaker.nl/time-nuts/DMTD%20self-noise%20OADEV%20with%20PLL%20and%20various%20filters.pdf
for this 600000-second recording:
http://www.lartmaker.nl/time-nuts/600ksec%20run%20with%20PLL,%2010811%20through%20splitter.png
<
http://www.lartmaker.nl/time-nuts/600ksec%20run%20with%20PLL,%2010811%20through%20splitter.png
. OADEV past ~1000sec is severely compromised by the fact that the
measurement setup is in my home lab which sees temperature swings of
up
to
20 degrees C and which does get bumped from time to time. Longer
runs in
a
more controlled setting forthcoming).
I can offer an explanation for the large effect of the zero
correction seen
here. The LTC2140 is specified to have a +/-10µV/°C drift (at 1Vpp
setting).
Converted into phase error due to zero crossing shift, this turns into
a phase shift of +/-1ps/°C @ 10MHz. Note, the shift is given as +/-
and
per channel, which means, it could very well be that the channels are
not matched in their temperature characteristics and thus the total
phase
shift could be +/-2ps/°C ... though total shift being closer to
0.5ps/°C is
more likely.
Summa sumarum: DC offset correction is important if a zero crossing
detector is used.
Attila Kinali
--
<JaberWorky> The bad part of Zurich is where the degenerates
throw DARK chocolate at you.
time-nuts mailing list -- time-nuts@lists.febo.com <mailto:
To unsubscribe, go to
http://lists.febo.com/mailman/listinfo/time-nuts_lists.febo.com <
To unsubscribe, go to
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http://lists.febo.com/mailman/listinfo/time-nuts_lists.febo.com>
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To unsubscribe, go to
and follow the instructions there.
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To unsubscribe, go to
and follow the instructions there.
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To unsubscribe, go to
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and follow the instructions there.