Contents of the latest issue of: *International Journal of Embedded and Real-Time Communication Systems (IJERTCS)* Official Publication of the Information Resources Management Association Volume 1, Issue 3, July-September 2010 Published: Quarterly in Print and Electronically ISSN: 1947-3176 EISSN: 1947-3184 Published by IGI Publishing, Hershey-New York, USA www.igi-global.com/ijertcs Editor-in-Chief: Seppo Virtanen, University of Turku, Finland *EDITORIAL PREFACE* System-on-Chip for Embedded Communication Systems I Jari Nurmi, Tampere University of Technology, Finland To view the editorial preface, please click on the link below. <http://igi-global.com/Bookstore/TitleDetails.aspx?TitleId=45823> *PAPER ONE* Automatic Generation of Memory Interfaces for ASIPs David Kammler, RWTH Aachen University, Germany Ernst Witte, RWTH Aachen University, Germany Anupam Chattopadhyay, RWTH Aachen University, Germany Bastian Bauwens, RWTH Aachen University, Germany Gerd Ascheid, RWTH Aachen University, Germany Rainer Leupers, RWTH Aachen University, Germany Heinrich Meyr, RWTH Aachen University, Germany With the growing market for multi-processor system-on-chip (MPSoC) solutions, application-specific instruction-set processors (ASIPs) gain importance as they allow for a wide tradeoff between flexibility and efficiency in such a system. Their development is aided by architecture description languages (ADLs) supporting the automatic generation of architecture-specific tool sets as well as synthesizable register transfer level (RTL) implementations from a single architecture model. However, these generated implementations have to be manually adapted to the interfaces of dedicated memories or memory controllers, slowing down the design-space exploration regarding the memory architecture. To overcome this drawback, the authors extend RTL code generation from ADL models with the automatic generation of memory interfaces. This is accomplished by introducing a new abstract and versatile description format for memory interfaces and their timing protocols. The feasibility of this approach is demonstrated in real-life case studies, including a design space exploration for a banked memory system. To obtain a copy of the entire article, click on the link below. <http://igi-global.com/Bookstore/Article.aspx?TitleId=45870> *PAPER TWO* Implementation of FFT on General-Purpose Architectures for FPGA Fabio Garzia, Tampere University of Technology, Finland Roberto Airoldi, Tampere University of Technology, Finland Jari Nurmi, Tampere University of Technology, Finland This paper describes two general-purpose architectures targeted to Field Programmable Gate Array (FPGA) implementation. The first architecture is based on the coupling of a coarse-grain reconfigurable array with a general-purpose processor core. The second architecture is a homogeneous multi-processor system-on-chip (MP-SoC). Both architectures have been mapped onto two different Altera FPGA devices, a StratixII and a StratixIV. Although mapping onto the StratixIV results in higher operating frequencies, the capabilities of the device are not fully exploited. The implementation of a FFT on the two platforms shows a considerable speed-up in comparison with a single-processor reference architecture. The speed-up is higher in the reconfigurable solution but the MP-SoC provides an easier programming interface that is completely based on C language. The authors’ approach proves that implementing a programmable architecture on FPGA and then programming it using a high-level software language is a viable alternative to designing a dedicated hardware block with a hardware description language (HDL) and mapping it on FPGA. To obtain a copy of the entire article, click on the link below. <http://igi-global.com/Bookstore/Article.aspx?TitleId=45871> *PAPER THREE* System Architecture for 3GPP-LTE Modem using a Programmable Baseband Processor Di Wu, Linköping University, Sweden Johan Eilert, Linköping University, Sweden Rizwan Asghar, Linköping University, Sweden Dake Liu, Linköping University, Sweden Anders Nilsson, Coresonic AB, Sweden Eric Tell, Coresonic AB, Sweden Eric Alfredsson, Coresonic AB, Sweden The evolution of third generation mobile communications toward high-speed packet access and long-term evolution is ongoing and will substantially increase the throughput with higher spectral efficiency. This paper presents the system architecture of an LTE modem based on a programmable baseband processor. The architecture includes a baseband processor that handles processing time and frequency synchronization, IFFT/FFT (up to 2048-p), channel estimation and subcarrier de-mapping. The throughput and latency requirements of a Category four User Equipment (CAT4 UE) is met by adding a MIMO symbol detector and a parallel Turbo decoder supporting H-ARQ, which brings both low silicon cost and enough flexibility to support other wireless standards. The complexity demonstrated by the modem shows the practicality and advantage of using programmable baseband processors for a single-chip LTE solution. To obtain a copy of the entire article, click on the link below. <http://igi-global.com/Bookstore/Article.aspx?TitleId=45872> ***************************************************** For full copies of the above articles, check for this issue of the *International Journal of Embedded and Real-Time Communication Systems (IJERTCS) *in your institution's library. This journal is also included in the IGI Global aggregated "*InfoSci-Journals*" database: http://www.igi-global.com/EResources/InfoSciJournals.aspx. ** ***************************************************** *CALL FOR PAPERS* Mission of IJERTCS: The mission of the *International Journal of Embedded and Real-Time Communication Systems (IJERTCS)* is to disseminate recent advancements and innovations in this interdisciplinary research area for field researchers, practitioners, scientists, academicians, students, and IT professionals. IJERTCS focuses on overcoming challenges involved in the rapid development of embedded communication systems towards feature-rich multimedia computers Coverage of IJERTCS: The *International Journal of Embedded and Real-Time Communication Systems (IJERTCS)* extensively covers research in the area of embedded and real-time communication systems. Within this field, topics to be discussed in the journal include (but are not limited to) the following: Asynchronous and synchronous circuit techniques Design methods Embedded networks (built-in networks in embedded communication devices) Emerging new topics Fault-tolerant hardware and software technologies Formal design and verification methods Hardware and software solutions for protocol processing Hardware and software solutions for real-time systems Hardware platforms and technologies Hardware/software co-design Modeling and verification methods On-chip communication in SoC and NoC OWA (open wireless architecture) Performance modeling Platform based design Real-time computing Reconfigurable systems Security issues and technologies Single-chip SDR (software defined radio) solutions Software design Testing techniques Interested authors should consult the journal's manuscript submission guidelines at www.igi-global.com/ijertcs <http://www.igi-global.com/ijertcs> All inquiries and submissions should be sent to: Editor-in-Chief: Seppo Virtanen at seppo.virtanen@utu.fi <mailto:seppo.virtanen@utu.fi>