Sub Pico Second Phase logger
Bruce
asked)
Doesn't this phase detector, like all digital phase detectors, have
significant non linearity at the ends of its range?
In the case of an XOR gate phase detector this is caused by the finite
slew rate of the gate output.
Thanks for all the ideas and Information.
True, XORs don't work good at the end of their range for several reasions.
This is why I had to put in the second pair of detectors.
K1 and K2 are used in the example as a sort of "smooth linear demulplexer"
to switch between the phase detectors. As one set of differential
phase detectors gets near its nonlinear and troublesome range at their zero
and 180 phase point their output change contribution is COMPLETELY shut down
by the a "sin" like function product of K and Phase#. Not really a sin
function and not really done as K's. The function of the sum of the two
phase detectors will be dependent on the voltages themself.
That is their modified voltage out will have less effect the farther away
from zero their phase voltage is. A smooth clipper function.
For a given detector pair the farther from zero it is the less its change
will contrubute. When both the zero and 90 degree phase detectors
are half way between zero and rail, their outputs gets summed together
with a weighing factor of 1/2 each.
One disadvantage of the quad phase detectors, is to work good and
allow the digital processing functions I want to have, there has to be two
seperate data paths, one from each Pair of phase detectors.
The data rate is slow enough even with the desired oversampling
that a multiplexed ADC my be OK.
Is there anything that cares about faster than about 10Hz high resolution
phase update times, that a simple analog XOR phase detector could handle?
Also I do not think that the linearity has to be very good. I was thinking if
it stays within say 90% it would be good enough for what I know of. The important
thing is Just so it stays monotonic and glitch free with no hysteresis etc which
it seems to do. It is not 1 million to one accurate as you know, maybe more like
within 1% or 0.1%. The one I build only has a million to one resolution
around 90, 270 degs, zero and 180 deg. which is the only place I generally using it.
At the moment the accuracy and noise performance with the detector away
from its zero output value is limited by the accuracy of the reference along
with a lot of other gain error things.
Is there any use for a truly linear and accurate simple phase detector?
I supose it could be done, in a similar mater, but may have to add a couple parts.
You also said HCMOS buffers have 4ps or so of jitter. Is this the kind of jitter noise
that can be filtered down into the mud with the present 100ms analog Bandwidth
and the 250K samples that are effectively being averaging?
Do you have any knowledge or guess on ICs NON tracking delay change with Temp?
I've tried to match all delays in the four loops, by always having a part from the same
IC in each loop, so mostly, as long as all like parts in any single IC track well then their
zero errors should cancel.
I have not tested it much below 1ps except to see what I think was more like 0.1 ps resolution.
The test I did for that was to move my hand near the center of one channel's shielded
signal cable the watched the phase output smoothly change like a proximity detector
as my hand approached the shielded cable, not due to cap to ground but due to the
cable delay changing. Thoses electrons just don't get very far in 100fs
I am considering using a faster famly, but I do want to say away from anything that
produces any heat. It looks like temperture offsets and changes are going to be the
limiting factor for zero stability.
I use the same dual detector design to phase lock now, but I never have checked or
cared how good it can get.
Thanks for the review and feedback, I've added several questions, please comment where you can?
I'm planning to make another pass at it and clean it up for thermos etc. and see how low it will go.
Concerning other uses of the single differential XOR phase detector.
If anyone wants to improve the performance of an existing crappy XOR phase detector
they may want to consider the differential XOR detector. Just be sure to include a good differential
integrator (with a zero pole) at its output before driving the EFC so that the phase detector's
output always stays at zero. The differential detector can reduce phase detector errors
by many orders of magnitude.
WarrenS
Bruce Griffiths bruce.griffiths at xtra.co.nz
Fri Dec 5 05:09:53 UTC 2008
a.. Previous message: [time-nuts] Sub Pico Second Phase logger
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WarrenS wrote:
Building a Sub Pico Second phase detector.
I was inspired to build this project yesterday after downloading and trying
Ulrich Bangert's 'DF6JB's Plotter 2008-10-10' program with its unbelievable
flexible user Interface capabilities. http://www.ulrich-bangert.de/html/downloads.html
What I needed was a Phase detector to use with the 'Plotter' program.
I decided to see what it takes to build a simple high resolution, sub Pico second,
linear phase logging detector using standard off the self IC's.
How If works:
The 5 or 10 MHz signal to be measured is buffered and toggles a
synchronous divide by two or four FF. This gives a 2.5MHz square wave and its complement.
Each side of the flip-flop connects to two of four XOR gates.
The 10 MHz reference signal goes thru a matching buffer and then to a pair of synchronous
Flip-Flops that provide a zero and a 90 deg phase shifted 2.5MHz square wave.
Each of these goes to two inputs of the XOR gates. The four XOR phase detectors
are connected to give four PWM type XOR phase detectors, each separate by 90 deg.
Each of the four XOR outputs are buffered by a cmos buffer gate
that has been powered by it's own 5 volt reference supply.
The buffer outputs then goes thru a multi-stage passive RC filter set up to
give two differential filtered PASSIVE + - 5 volt outputs, 90 deg apart.
Logging Data:
For the most flexible and best performance, two differential 16 plus bit ADC's
should be used, each connected to one of the dual differential Phase detectors.
After using the appropriate Analog RC filters, oversampling, digital filters, and digital
scaling, you get a file with a single column of data to feed "Plotter" the phase
difference of the two 10 MHz signals.
The Data scaling and processing:
For simple controlled short term or lower resolution data taking a PC Multimeter,
if it is isolated so that you can use it differentially will work. If not you need to add a differential amp.
For best performance, process the phase data from the two differential phase detectors
through two identical digital filter algorithms.
Doing this real time on a PC or after all the data is recorder on a XL spread sheet both work for me.
Besides the filtering, the spread sheet or PC needs to also do the linearizing by
( K1* Phase1_Data) + (K2 * Phase2_Data).
K1 and K2 are the sine value of their respective Phase detectors.
One of the several tricks to why this can provide orders of magnitude better
performance than is generally obtained from similar type phase detectors
is because of the four matched Phase detectors that are added, subtracted
and combined and linerized in such a way as to cancel the type of errors
found in single XOR phase detectors.
Preliminary Performance
The noise floor that I have seen while feeding the same low noise osc, to both inputs,
is around 10 uv peak to peak at low Bandwidths, at zero phase, using a 6 digit DVM
with a slow filter which corresponds to <<1 ps. Test are still underway to see what the
lower limit is, and what the sensitivity to the environment is.
This is just the start of an on going learning project, It is just at the breadboard stage and
needs to be verified, critiqued, cleaned up and packaged up.
Noted that when working with sub ps resolution, extra care needs to be taken.
Although it looks to be a standard digital circuit, It is not. It is a very sensitive Analog circuit
capable of giving 1 part in a million type of resolution. It can resolve path distance changes
in the 1/100 to 1/1000 of an inch, and needs to be built with care and 'respect'.
Another use (beside watching just how noisy your "GOOD " osc is),
It can be used to compare and adjust the freq differences between two osc
very quickly and with more resolution than most can use.
1 E-12 freq difference gave several counts per second change on
the DVM, and with the DVM updating at several times a second,
it made fine freq adjustments much easer than slower monitoring ways.
If you know of other simple high resolution phase detectors,
or see any problems or improvements
with the idea, I'd like to hear from you.
Have fun
WarrenS
Warren
Since HCMOS buffers typically have about 4ps of random propagation delay
jitter and ACMOS devices typically have about 1ps of RJ this isnt too
surprising.
Newer logic families may have even lower random jitter.
Doesn't this phase detector, like all digital phase detectors, have
significant non linearity at the ends of its range?
In the case of an XOR gate phase detector this is caused by the finite
slew rate of the gate output.
With the quadrature phased outputs at least 2 of the phase detectors
will be operating in the linear part of their range.
The particular pair that are linear depends on the relative phase of the
2 inputs.
One or more of the ubiquitous 24 bit resolution sigma delta ADCs with
differential inputs and a reference derived from the XOR power supply,
will for CMOS XOR gates probably be a relatively inexpensive replacement
for the DVM int he final system.
If one used an FPGA or CPLD for this as the internal crosstalk may limit
performance to a few tens of picosec noise for 1 sec averaging unless
differential I/O logic such as LDVS, ECL etc are used.
Although the circuit is simple enough not to warrant an FPGA it would be
useful to have programmable dividers for each input to allow comparison
of input frequencies that arent either nominally equal or have a
frequency ratio of 2:1. Using external retiming flipflops should cure
the crosstalk problem with such a divider.
In practice such a divider should perhaps be an external device with its
own power supply and enclosure.
Such a divider can be used to increase the effective range of the phase
detector at the expense of its resolution.
Bruce
Warren
Bruce
asked)
Doesn't this phase detector, like all digital phase detectors, have
significant non linearity at the ends of its range?
In the case of an XOR gate phase detector this is caused by the finite
slew rate of the gate output.
Thanks for all the ideas and Information.
True, XORs don't work good at the end of their range for several reasions.
This is why I had to put in the second pair of detectors.
K1 and K2 are used in the example as a sort of "smooth linear demulplexer"
to switch between the phase detectors. As one set of differential
phase detectors gets near its nonlinear and troublesome range at their zero
and 180 phase point their output change contribution is COMPLETELY shut down
by the a "sin" like function product of K and Phase#. Not really a sin
function and not really done as K's. The function of the sum of the two
phase detectors will be dependent on the voltages themself.
That is their modified voltage out will have less effect the farther away
from zero their phase voltage is. A smooth clipper function.
For a given detector pair the farther from zero it is the less its change
will contrubute. When both the zero and 90 degree phase detectors
are half way between zero and rail, their outputs gets summed together
with a weighing factor of 1/2 each.
One disadvantage of the quad phase detectors, is to work good and
allow the digital processing functions I want to have, there has to be two
seperate data paths, one from each Pair of phase detectors.
The data rate is slow enough even with the desired oversampling
that a multiplexed ADC my be OK.
Multiplexing a sigma delta ADC inputs only works well if the ADC design
is appropriate.
Linear technology have some especially designed for use with multiplexed
inputs.
Sigma delta ADCs are relatively inexpensive so one could always use a
couple of them.
Surely the outputs of both phase detectors are required to sort out the
the sign/direction of phase changes?
One could always log both outputs and sort out the sign of any changes
together with the appropriate output to use for determining the
magnitude in software.
Is there anything that cares about faster than about 10Hz high resolution
phase update times, that a simple analog XOR phase detector could handle?
Also I do not think that the linearity has to be very good. I was thinking if
it stays within say 90% it would be good enough for what I know of. The important
thing is Just so it stays monotonic and glitch free with no hysteresis etc which
it seems to do. It is not 1 million to one accurate as you know, maybe more like
within 1% or 0.1%. The one I build only has a million to one resolution
around 90, 270 degs, zero and 180 deg. which is the only place I generally using it.
At the moment the accuracy and noise performance with the detector away
from its zero output value is limited by the accuracy of the reference along
with a lot of other gain error things.
Is there any use for a truly linear and accurate simple phase detector?
I supose it could be done, in a similar mater, but may have to add a couple parts.
Only when one uses such a phase detector to measure the frequency offset
between the 2 sources being compared as quickly and accurately as possible.
The principal source of non linearity near the ends of the range is due
to insufficient time available for the transitions to settle accurately
with short pulse widths.
If the value of the first resistor in the RC passive filter is too low
the output resistance mismatch between the 0 and 1 states will
contribute significantly to the nonlinearity.
Modulation of the output resistance of the gate/buffer driving the RC
filter can also be significant.
Both of these effects can easily be reduced to insignificance by using
appropriate feedback circuitry.
You also said HCMOS buffers have 4ps or so of jitter. Is this the kind of jitter noise
that can be filtered down into the mud with the present 100ms analog Bandwidth
and the 250K samples that are effectively being averaging?
Do you have any knowledge or guess on ICs NON tracking delay change with Temp?
Random jitter will indeed average down to the femtosecond level with
that many samples.
A crude way of estimating the propagation delay mismatch tempco for CMOS
ICs is to assume that the propagation delay mismatch has the same tempco
as the propagation delay itself or about +0.4%/C.
e.g. if the propagation delay is say 10ns and the mismatch is 10% (1ns)
then the delay mismatch tempco will be in the region of 4ps/C.
I've tried to match all delays in the four loops, by always having a part from the same
IC in each loop, so mostly, as long as all like parts in any single IC track well then their
zero errors should cancel.
I have not tested it much below 1ps except to see what I think was more like 0.1 ps resolution.
The test I did for that was to move my hand near the center of one channel's shielded
signal cable the watched the phase output smoothly change like a proximity detector
as my hand approached the shielded cable, not due to cap to ground but due to the
cable delay changing. Thoses electrons just don't get very far in 100fs
I am considering using a faster famly, but I do want to say away from anything that
produces any heat. It looks like temperture offsets and changes are going to be the
limiting factor for zero stability.
If the power dissipation is low it would be feasible to use a
bootstrapped oven (similar in thermal design to some of the standard
cell oven designs from the 50's and 60's) like Wenzel has used to
achieve sup-picosecond stability in a frequency multiplier.
I use the same dual detector design to phase lock now, but I never have checked or
cared how good it can get.
Thanks for the review and feedback, I've added several questions, please comment where you can?
I'm planning to make another pass at it and clean it up for thermos etc. and see how low it will go.
Concerning other uses of the single differential XOR phase detector.
If anyone wants to improve the performance of an existing crappy XOR phase detector
they may want to consider the differential XOR detector. Just be sure to include a good differential
integrator (with a zero pole) at its output before driving the EFC so that the phase detector's
output always stays at zero. The differential detector can reduce phase detector errors
by many orders of magnitude.
WarrenS
Bruce
WarrenS wrote:
Bruce
asked)
Doesn't this phase detector, like all digital phase detectors, have
significant non linearity at the ends of its range?
In the case of an XOR gate phase detector this is caused by the finite
slew rate of the gate output.
Thanks for all the ideas and Information.
True, XORs don't work good at the end of their range for several reasions.
This is why I had to put in the second pair of detectors.
K1 and K2 are used in the example as a sort of "smooth linear demulplexer"
to switch between the phase detectors. As one set of differential
phase detectors gets near its nonlinear and troublesome range at their zero
and 180 phase point their output change contribution is COMPLETELY shut down
by the a "sin" like function product of K and Phase#. Not really a sin
function and not really done as K's. The function of the sum of the two
phase detectors will be dependent on the voltages themself.
That is their modified voltage out will have less effect the farther away
from zero their phase voltage is. A smooth clipper function.
For a given detector pair the farther from zero it is the less its change
will contrubute. When both the zero and 90 degree phase detectors
are half way between zero and rail, their outputs gets summed together
with a weighing factor of 1/2 each.
One disadvantage of the quad phase detectors, is to work good and
allow the digital processing functions I want to have, there has to be two
seperate data paths, one from each Pair of phase detectors.
The data rate is slow enough even with the desired oversampling
that a multiplexed ADC my be OK.
Is there anything that cares about faster than about 10Hz high resolution
phase update times, that a simple analog XOR phase detector could handle?
Also I do not think that the linearity has to be very good. I was thinking if
it stays within say 90% it would be good enough for what I know of. The important
thing is Just so it stays monotonic and glitch free with no hysteresis etc which
it seems to do. It is not 1 million to one accurate as you know, maybe more like
within 1% or 0.1%. The one I build only has a million to one resolution
around 90, 270 degs, zero and 180 deg. which is the only place I generally using it.
At the moment the accuracy and noise performance with the detector away
from its zero output value is limited by the accuracy of the reference along
with a lot of other gain error things.
Is there any use for a truly linear and accurate simple phase detector?
I supose it could be done, in a similar mater, but may have to add a couple parts.
You also said HCMOS buffers have 4ps or so of jitter. Is this the kind of jitter noise
that can be filtered down into the mud with the present 100ms analog Bandwidth
and the 250K samples that are effectively being averaging?
Do you have any knowledge or guess on ICs NON tracking delay change with Temp?
I've tried to match all delays in the four loops, by always having a part from the same
IC in each loop, so mostly, as long as all like parts in any single IC track well then their
zero errors should cancel.
I have not tested it much below 1ps except to see what I think was more like 0.1 ps resolution.
The test I did for that was to move my hand near the center of one channel's shielded
signal cable the watched the phase output smoothly change like a proximity detector
as my hand approached the shielded cable, not due to cap to ground but due to the
cable delay changing. Thoses electrons just don't get very far in 100fs
I am considering using a faster famly, but I do want to say away from anything that
produces any heat. It looks like temperture offsets and changes are going to be the
limiting factor for zero stability.
I use the same dual detector design to phase lock now, but I never have checked or
cared how good it can get.
Thanks for the review and feedback, I've added several questions, please comment where you can?
I'm planning to make another pass at it and clean it up for thermos etc. and see how low it will go.
Concerning other uses of the single differential XOR phase detector.
If anyone wants to improve the performance of an existing crappy XOR phase detector
they may want to consider the differential XOR detector. Just be sure to include a good differential
integrator (with a zero pole) at its output before driving the EFC so that the phase detector's
output always stays at zero. The differential detector can reduce phase detector errors
by many orders of magnitude.
WarrenS
Warren
Another potential issue is crosstalk between flipflops in the same
package, in particular between the 2 clock signals.
Such effects will not be evident when using a single clock source to
evaluate the system noise.
Using fully differential logic such as ECL will reduce such coupling at
the expense on increased power dissipation and relatively high logic
level tempcos.
Dithering one or both of the clocks may help.
Bruce
Bruce
Warren
Another potential issue is crosstalk between flipflops in the same
package, in particular between the 2 clock signals.
Such effects will not be evident when using a single clock source to
evaluate the system noise.
Using fully differential logic such as ECL will reduce such coupling at
the expense on increased power dissipation and relatively high logic
level tempcos.
Dithering one or both of the clocks may help.
Bruce
The effect of cross coupling between the clocks will be more significant
as the phase shift between the clocks approaches 0 or 180 degrees (for
50% duty cycle clocks).
Dividing the input frequencies by 4 to produce quadrature phase outputs
wont help.
You would need to actually use a pair of phase shifted clocks from one
of the input sources feeding separate dividers so that clock transitions
of the 2 clocks within a chip do not coincide.
Either a selected length of coax or a quadrature hybrid would suffice
for producing the 2 clocks with a near 90 degree phase shift.
Bruce
Warren
Another potential issue is crosstalk between flipflops in the same
package, in particular between the 2 clock signals.
Such effects will not be evident when using a single clock source to
evaluate the system noise.
Using fully differential logic such as ECL will reduce such coupling at
the expense on increased power dissipation and relatively high logic
level tempcos.
Dithering one or both of the clocks may help.
Bruce
The effect of cross coupling between the clocks will be more significant
as the phase shift between the clocks approaches 0 or 180 degrees (for
50% duty cycle clocks).
Dividing the input frequencies by 4 to produce quadrature phase outputs
wont help.
You would need to actually use a pair of phase shifted clocks from one
of the input sources feeding separate dividers so that clock transitions
of the 2 clocks within a chip do not coincide.
Either a selected length of coax or a quadrature hybrid would suffice
for producing the 2 clocks with a near 90 degree phase shift.
Bruce
A much simpler solution to the clock cross coupling problem is to use
separate chips for the 2 dividers and live with the less accurate delay
tracking.
One then has to ensure that significant cross coupling via the power
supply and ground systems doesnt occur.
Bruce
Bruce
Thanks, for pointing out my FF mistake. I do know that at this level of resolution
you can not have two edges that are close together in the same AIR Space,
let alone the same IC without some interaction.I would not put them on the same PCB or PS
when checking what the best possible resolution is.
I was thinking because of the dual 90 deg paths, the IC in which the
two phases got close together would not be used at that time anyway so it did not matter too much.
Obviously I blew it big time by forgetting to consider the first set of FFs whose edges can and do cross.
In my case this is not a problem because these FF are in fact on the reference osc and not in my breadboard.
& I messed up, Thanks for pointing what out.
The description I gave is not my present phase detector.
I include all the extra possibilities I could think of and some planned upgrades,
to make it into a more General purpose & flexible tool instead of the simple
one function tool it now is.
I need to remember the KISS concept. The best is the simple way.
For sub pico second measurement a single dual XOR differential phase detector is all that is needed.
All that extra stuff I is only needed if someone wanted to make a very general purpose
wide range less accurate XOR phase detector.
The trick to keeping it simple and accurate is the willingness to change the phase
of the low noise (2.5 MHz divided down) Osc to 90 deg offset at the start of the test.
The way I do it is: on my test OCXO Osc I have added a semi calibrated, 10 turn dial that I can
fine set its freq to 1 part in 1E-12 resolution.
It also has an added switch that allows the output of the dual differential sub pico second Phase detector
to change the phase of the test Osc in a short time period by way of the ECF.
Once the two signal are phase locked at 90 deg, indicated by the dual phase detector at zero volts out,
I open the lock phase switch, re-adjust the fine freq trim pot if necessary so that the phase detector does
not drift off too fast, and rezero the detector again with the switch when required, etc.
To record data, I set my cheap little isolated 4+ digit PC logable DVM to its mV range,
and log data at once per second which is good for as long as the phase detector's output
stays around zero. This all requires a manual set up, It takes a little extra time, BUT it gets the job done.
It is also Very cheap to build and it seems to perform better than most near 'state of the art' home equipment.
The whole thing takes 3 Ics including some extra non related stuffs.
Thanks for your feedback, If you see or think of anything else you feel would be helpful to me do please let me know.
WarrenS
Warren
Another potential issue is crosstalk between flipflops in the same
package, in particular between the 2 clock signals.
Such effects will not be evident when using a single clock source to
evaluate the system noise.
Using fully differential logic such as ECL will reduce such coupling at
the expense on increased power dissipation and relatively high logic
level tempcos.
Dithering one or both of the clocks may help.
Bruce
The effect of cross coupling between the clocks will be more significant
as the phase shift between the clocks approaches 0 or 180 degrees (for
50% duty cycle clocks).
Dividing the input frequencies by 4 to produce quadrature phase outputs
wont help.
You would need to actually use a pair of phase shifted clocks from one
of the input sources feeding separate dividers so that clock transitions
of the 2 clocks within a chip do not coincide.
Either a selected length of coax or a quadrature hybrid would suffice
for producing the 2 clocks with a near 90 degree phase shift.
Bruce
*******************************>
Warren
A much simpler solution to the clock cross coupling problem is to use
separate chips for the 2 dividers and live with the less accurate delay tracking.
One then has to ensure that significant cross coupling via the power
supply and ground systems doesn't occur.
Bruce
Warren
Bruce
asked)
Doesn't this phase detector, like all digital phase detectors, have
significant non linearity at the ends of its range?
In the case of an XOR gate phase detector this is caused by the finite
slew rate of the gate output.
Thanks for all the ideas and Information.
True, XORs don't work good at the end of their range for several reasions.
This is why I had to put in the second pair of detectors.
K1 and K2 are used in the example as a sort of "smooth linear demulplexer"
to switch between the phase detectors. As one set of differential
phase detectors gets near its nonlinear and troublesome range at their zero
and 180 phase point their output change contribution is COMPLETELY shut down
by the a "sin" like function product of K and Phase#. Not really a sin
function and not really done as K's. The function of the sum of the two
phase detectors will be dependent on the voltages themself.
That is their modified voltage out will have less effect the farther away
from zero their phase voltage is. A smooth clipper function.
For a given detector pair the farther from zero it is the less its change
will contrubute. When both the zero and 90 degree phase detectors
are half way between zero and rail, their outputs gets summed together
with a weighing factor of 1/2 each.
One disadvantage of the quad phase detectors, is to work good and
allow the digital processing functions I want to have, there has to be two
seperate data paths, one from each Pair of phase detectors.
The data rate is slow enough even with the desired oversampling
that a multiplexed ADC my be OK.
Multiplexing a sigma delta ADC inputs only works well if the ADC design
is appropriate.
Linear technology have some especially designed for use with multiplexed
inputs.
Sigma delta ADCs are relatively inexpensive so one could always use a
couple of them.
Surely the outputs of both phase detectors are required to sort out the
the sign/direction of phase changes?
One could always log both outputs and sort out the sign of any changes
together with the appropriate output to use for determining the
magnitude in software.
Is there anything that cares about faster than about 10Hz high resolution
phase update times, that a simple analog XOR phase detector could handle?
Also I do not think that the linearity has to be very good. I was thinking if
it stays within say 90% it would be good enough for what I know of. The important
thing is Just so it stays monotonic and glitch free with no hysteresis etc which
it seems to do. It is not 1 million to one accurate as you know, maybe more like
within 1% or 0.1%. The one I build only has a million to one resolution
around 90, 270 degs, zero and 180 deg. which is the only place I generally using it.
At the moment the accuracy and noise performance with the detector away
from its zero output value is limited by the accuracy of the reference along
with a lot of other gain error things.
Is there any use for a truly linear and accurate simple phase detector?
I supose it could be done, in a similar mater, but may have to add a couple parts.
Only when one uses such a phase detector to measure the frequency offset
between the 2 sources being compared as quickly and accurately as possible.
The principal source of non linearity near the ends of the range is due
to insufficient time available for the transitions to settle accurately
with short pulse widths.
If the value of the first resistor in the RC passive filter is too low
the output resistance mismatch between the 0 and 1 states will
contribute significantly to the nonlinearity.
Modulation of the output resistance of the gate/buffer driving the RC
filter can also be significant.
Both of these effects can easily be reduced to insignificance by using
appropriate feedback circuitry.
You also said HCMOS buffers have 4ps or so of jitter. Is this the kind of jitter noise
that can be filtered down into the mud with the present 100ms analog Bandwidth
and the 250K samples that are effectively being averaging?
Do you have any knowledge or guess on ICs NON tracking delay change with Temp?
Random jitter will indeed average down to the femtosecond level with
that many samples.
A crude way of estimating the propagation delay mismatch tempco for CMOS
ICs is to assume that the propagation delay mismatch has the same tempco
as the propagation delay itself or about +0.4%/C.
e.g. if the propagation delay is say 10ns and the mismatch is 10% (1ns)
then the delay mismatch tempco will be in the region of 4ps/C.
I've tried to match all delays in the four loops, by always having a part from the same
IC in each loop, so mostly, as long as all like parts in any single IC track well then their
zero errors should cancel.
I have not tested it much below 1ps except to see what I think was more like 0.1 ps resolution.
The test I did for that was to move my hand near the center of one channel's shielded
signal cable the watched the phase output smoothly change like a proximity detector
as my hand approached the shielded cable, not due to cap to ground but due to the
cable delay changing. Thoses electrons just don't get very far in 100fs
I am considering using a faster famly, but I do want to say away from anything that
produces any heat. It looks like temperture offsets and changes are going to be the
limiting factor for zero stability.
If the power dissipation is low it would be feasible to use a
bootstrapped oven (similar in thermal design to some of the standard
cell oven designs from the 50's and 60's) like Wenzel has used to
achieve sup-picosecond stability in a frequency multiplier.
I use the same dual detector design to phase lock now, but I never have checked or
cared how good it can get.
Thanks for the review and feedback, I've added several questions, please comment where you can?
I'm planning to make another pass at it and clean it up for thermos etc. and see how low it will go.
Concerning other uses of the single differential XOR phase detector.
If anyone wants to improve the performance of an existing crappy XOR phase detector
they may want to consider the differential XOR detector. Just be sure to include a good differential
integrator (with a zero pole) at its output before driving the EFC so that the phase detector's
output always stays at zero. The differential detector can reduce phase detector errors
by many orders of magnitude.
WarrenS
WarrenS wrote:
Bruce
Thanks, for pointing out my FF mistake. I do know that at this level of resolution
you can not have two edges that are close together in the same AIR Space,
let alone the same IC without some interaction.I would not put them on the same PCB or PS
when checking what the best possible resolution is.
I was thinking because of the dual 90 deg paths, the IC in which the
two phases got close together would not be used at that time anyway so it did not matter too much.
Obviously I blew it big time by forgetting to consider the first set of FFs whose edges can and do cross.
In my case this is not a problem because these FF are in fact on the reference osc and not in my breadboard.
& I messed up, Thanks for pointing what out.
The description I gave is not my present phase detector.
I include all the extra possibilities I could think of and some planned upgrades,
to make it into a more General purpose & flexible tool instead of the simple
one function tool it now is.
I need to remember the KISS concept. The best is the simple way.
For sub pico second measurement a single dual XOR differential phase detector is all that is needed.
All that extra stuff I is only needed if someone wanted to make a very general purpose
wide range less accurate XOR phase detector.
The trick to keeping it simple and accurate is the willingness to change the phase
of the low noise (2.5 MHz divided down) Osc to 90 deg offset at the start of the test.
The way I do it is: on my test OCXO Osc I have added a semi calibrated, 10 turn dial that I can
fine set its freq to 1 part in 1E-12 resolution.
It also has an added switch that allows the output of the dual differential sub pico second Phase detector
to change the phase of the test Osc in a short time period by way of the ECF.
Once the two signal are phase locked at 90 deg, indicated by the dual phase detector at zero volts out,
I open the lock phase switch, re-adjust the fine freq trim pot if necessary so that the phase detector does
not drift off too fast, and rezero the detector again with the switch when required, etc.
To record data, I set my cheap little isolated 4+ digit PC logable DVM to its mV range,
and log data at once per second which is good for as long as the phase detector's output
stays around zero. This all requires a manual set up, It takes a little extra time, BUT it gets the job done.
It is also Very cheap to build and it seems to perform better than most near 'state of the art' home equipment.
The whole thing takes 3 Ics including some extra non related stuffs.
Thanks for your feedback, If you see or think of anything else you feel would be helpful to me do please let me know.
WarrenS
Warren
Some commercial instruments share flipflops in the same package between
2 channels each with a slightly different clock frequency.
The crosstalk between channels is largely capacitive in nature and can
be canceled to some extent by injecting a small portion of the
(antiphase) clock, crosstalk from which is to be canceled, via a
capacitor (of appropriate value). Whilst some improvement is possible
this isnt a complete cure.
For the less stable oscillators, dividing down the frequencies before
comparison with the limited range XOR phase detector is desirable if
they are to be monitored over a relatively long time.
HP used to make the K34-5991A phase comparator that used an ECL XOR
phase comparator.
This instrument was intended for driving a strip chart recorder.
It allowed the user to set the output to the ideal value for 180 degree
and zero degree phase shift between the inputs for calibration purposes.
Ratiometric conversion of the low pass filtered XOR output will reduce
the dependence of the measurement on power supply voltage.
Bruce