Moin, On 01/10/2016 07:56 PM, Attila Kinali wrote: > On Sun, 10 Jan 2016 14:30:41 +0100 > Magnus Danielson <magnus@rubidium.dyndns.org> wrote: > >>> SR-flipflop? Are you refering to the JK-FF phase detector or the PFD? >> >> A straight SR-flipflop. I would have written JK-FF or PFD if I meant it. >> Also, as I mentioned the PFD directly after, you could have concluded >> that was not what I intended. >> >> A SR-flip-flop with no illegal input states is easy to build from a 74HC00. > > The illegal input states were my concern, indeed. And a quick google > didn't show up anything to disperse these....not until I started reading > the 4046 datasheet in detail. That's one place to look yes. > But there is one thing about the arangement of the SR FF in the 4046[1] > that bothers me: > Although S = R = 1 is valid, it does lead to the output oscillating > between 0 and 1. Well, the dynamics of the gates will convert the rising edges on S and R into short pulses before hitting the SR core. That is what the additional AND gates does if you look at figure 1. The pulses on Sd and Rd will be about three gate-delays long. If the Sd and Rd '1' pulses overlap, then it becomes a bit hairer to analyze the stability. However, this works pretty well in reality. Rather than having the +/- 90 degree property of the XOR gate (which has a triangle phase-response, which doesn't always is helpful) it has a +/- 180 degree sawtooth phase-response. Cheers, Magnus

Hi Thanks to all the information here. I can put more items to my experiment list. Regads Li Ang, BI7LNQ 2016-01-11 11:28 GMT+08:00 Magnus Danielson <magnus@rubidium.dyndns.org>: > Moin, > > On 01/10/2016 07:56 PM, Attila Kinali wrote: > >> On Sun, 10 Jan 2016 14:30:41 +0100 >> Magnus Danielson <magnus@rubidium.dyndns.org> wrote: >> >> SR-flipflop? Are you refering to the JK-FF phase detector or the PFD? >>>> >>> >>> A straight SR-flipflop. I would have written JK-FF or PFD if I meant it. >>> Also, as I mentioned the PFD directly after, you could have concluded >>> that was not what I intended. >>> >>> A SR-flip-flop with no illegal input states is easy to build from a >>> 74HC00. >>> >> >> The illegal input states were my concern, indeed. And a quick google >> didn't show up anything to disperse these....not until I started reading >> the 4046 datasheet in detail. >> > > That's one place to look yes. > > But there is one thing about the arangement of the SR FF in the 4046[1] >> that bothers me: >> Although S = R = 1 is valid, it does lead to the output oscillating >> between 0 and 1. >> > > Well, the dynamics of the gates will convert the rising edges on S and R > into short pulses before hitting the SR core. That is what the additional > AND gates does if you look at figure 1. > > The pulses on Sd and Rd will be about three gate-delays long. > > If the Sd and Rd '1' pulses overlap, then it becomes a bit hairer to > analyze the stability. > > However, this works pretty well in reality. Rather than having the +/- 90 > degree property of the XOR gate (which has a triangle phase-response, which > doesn't always is helpful) it has a +/- 180 degree sawtooth phase-response. > > Cheers, > Magnus > > _______________________________________________ > time-nuts mailing list -- time-nuts@febo.com > To unsubscribe, go to > https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts > and follow the instructions there. >