Hi,

I would like to build an fpga custom fpga image for x410. I would need to be able to TX/RX anywhere between 250 to 300 MHz. The prebuilt UC_200 is too low and the CG_400 can’t be adjusted and a bit overkill. Any recommendations on how to best do that? Which version of Vivado would I need? I currently am using UHD 4.7 and have Vivado 2023.1 installed on my machine. I was wondering if its possible to tweak the UC_200 prebuilt image to do that? Thanks

Hi,

Thanks for the recommendations. I installed Vivado 2021.1 on my machine and ran the rfnoc_image_builder command found in the documentation using the yaml file x410_CG_400_rfnoc_image_core.yml. It generates a folder build-usrp_x410_fpga_CG_400 with the following files: device_tree.dts  Makefile.inc  rfnoc_image_core.sv  rfnoc_image_core.vh

How do I generate the bit fpga image file with this to load onto the x410?

Hi,

the rfnoc_image_builder has probably generated the bitfile but in a folder which you do not expect.

Until UHD 4.7 (which you are using), the build folder is generated in the same folder as the x410_CG_400_rfnoc_image_core.yml file (fpga/usrp3/top/x400) per default.

Starting with UHD 4.8, the “build” folder which contains the resulting .bit is generated in the current folder where run the “rfnoc_image_builder” command.
This change was introduced with commit 8e780be0, and described as follows:

image builder: create build(...) directories in the current directory
Introduce a new parameter --base-dir BASE_DIR.

If the parameters --build-dir BUILD_DIR / --build-ip-dir BUILD_IP_DIR
/ --build-output-dir BUILD_OUTPUT_DIR are not set explicitly, they will
be set to these values per default:

- BUILD_DIR=<BASE_DIR>/build-<IMAGE_CORE_NAME>
- BUILD_IP_DIR=<BASE_DIR>/build-ip
- BUILD_OUTPUT_DIR=<BASE_DIR>/build

BASE_DIR defaults to the current directory if the parameter --base-dir
is not set. This means that per default, the build(...) directories
are generated in the current directory.

Hi, thanks for the reply. I’m using UHD 4.7. I ran the following and it worked fine:

$ source ../setupenv.sh  --vivado-path=/opt/tools/Xilinx/Vivado/

Setting up a 64-bit FPGA build environment for the USRP-X4xx...

- Vivado: Found (/opt/tools/Xilinx/Vivado//2021.1/bin)

      Installed version is Vivado v2021.1_AR76780 (64-bit)

Environment successfully initialized.

However, from there, I ran rfsoc_image_builder:


$ rfnoc_image_builder -y x410_CG_400_rfnoc_image_core.yml -t x410_CG_400 --vivado-path /opt/tools/Xilinx/Vivado/

Using FPGA directory /home/computer/uhd/fpga

Selected device: x410

Launching build with the following settings:

* FPGA Directory: /home/computer/uhd/fpga/usrp3/top/x400

* Build Artifacts Directory: /home/computer/uhd/fpga/usrp3/top/x400/build-usrp_x410_fpga_CG_400

* Build Output Directory: /home/computer/uhd/fpga/usrp3/top/x400/build

* Build IP Directory: /home/computer/uhd/fpga/usrp3/top/x400/build-ip

Executing the following command: /bin/bash -c ". ./setupenv.sh --vivado-path=/opt/tools/Xilinx/Vivado/ && make x410_CG_400 BUILD_DIR=/home/computer/uhd/fpga/usrp3/top/x400/build-usrp_x410_fpga_CG_400 IMAGE_CORE_NAME=usrp_x410_fpga_CG_400"

Setting up a 64-bit FPGA build environment for the USRP-X4xx...

- Vivado: Found (/opt/tools/Xilinx/Vivado//2021.1/bin)

      Installed version is Vivado v2021.1_AR76780 (64-bit)

Environment successfully initialized.

make: *** No rule to make target 'x410_CG_400'.  Stop.

I’m guessing its supposed to make the .bit file but not able to. I also tried running the Makefile.inc in the build folder (make -f Makefile.inc)
$ make -f Makefile.inc

make: *** No targets.  Stop.

This is what it looks like:
LIB_DIR := $(HOME)/uhd/fpga/usrp3/lib

include $(LIB_DIR)/rfnoc/blocks/rfnoc_block_radio/Makefile.srcs

include $(LIB_DIR)/hwutils/Makefile.srcs

include $(LIB_DIR)/rfnoc/transport_adapters/rfnoc_ta_x4xx_eth/Makefile.srcs

include $(LIB_DIR)/rfnoc/transport_adapters/rfnoc_ta_chdr_dma/Makefile.srcs

RFNOC_XDC_SRCS = \

constraints/pins/qsfp0_0.xdc \

constraints/pins/qsfp0_1.xdc \

constraints/pins/qsfp0_2.xdc \

constraints/pins/qsfp0_3.xdc \

constraints/pins/qsfp1_0.xdc \

constraints/pins/qsfp1_1.xdc \

constraints/pins/qsfp1_2.xdc \

constraints/pins/qsfp1_3.xdc \

RFNOC_IMAGE_CORE_SRCS += $(abspath \

$(BUILD_DIR)/rfnoc_image_core.sv \

$(RFNOC_CORE_HEADERS) \

$(RFNOC_BLOCK_RADIO_SRCS) \

$(HWUTILS_SRCS) \

$(RFNOC_TA_X4XX_ETH_SRCS) \

$(RFNOC_TA_CHDR_DMA_SRCS) \

)

RFNOC_IMAGE_CORE_DEFS = RF_BW=400 RF_CORE_400M=1 DRAM_BANKS=0 DRAM_CH=0 DRAM_W=64 QSFP0_0=5 QSFP0_1=0 QSFP0_2=0 QSFP0_3=0 QSFP1_0=5 QSFP1_1=0 QSFP1_2=0 QSFP1_3=0


Any idea what the issue is?

Hi,

the correct value for the --target parameter when building for x410 is “X410”:

$ rfnoc_image_builder -y x410_CG_400_rfnoc_image_core.yml --target X410 --vivado-path /opt/tools/Xilinx/Vivado/

However, the image core file already includes the default target value, this means it is sufficient if you run:

$ rfnoc_image_builder -y x410_CG_400_rfnoc_image_core.yml --vivado-path /opt/tools/Xilinx/Vivado/

That worked for me. Thank you. However, I’m running into error at the end when its generating the bitstream:

[01:49:04] Starting Write Bitstream Command
ERROR: [Common 17-69] Command failed: This design contains one or more cells for which bitstream generation is not permitted:
[01:49:12] Current task: Write Bitstream +++ Current Phase: Starting
[01:49:13] Current task: Write Bitstream +++ Current Phase: Finished
[01:49:13] Process terminated. Status: Failure

Is this a licensing issue? I’m using the nodelocked trial license for Vivado_ML_Enterprise_Edition. Is there any other license I would need to download to generate the bitstream?