usrp-users@lists.ettus.com
Discussion and technical support related to USRP, UHD, RFNoC
View all threadsADC saturation problem in USRP X310
Hello,
I am currently facing an issue with ADC saturation on a USRP X310 equipped with a UBX daughterboard. We are conducting measurements using an LTE signal and a sinusoidal input signal, but it seems that the ADC is saturating, leading to a loss of dynamic range in our measurements.
Test context:
We are transmitting (using a generator) an LTE signal with a power of -50 dBm at a center frequency of 1815 MHz. Then, we add a sinusoidal signal at 1865 MHz with a power of -30 dBm. This second, more powerful signal seems to be causing the ADC to saturate, even though we don’t see it directly in the IQ samples due to the digital filtering applied downstream.
Problem:
We suspect that the ADC saturation occurs before IQ conversion and is therefore masked by the digital filters. This results in a loss of dynamic range in our measurements, and we feel that adjusting the gain based on the IQ samples may not be reliable.
Question:
How can this ADC saturation be detected upstream of the IQ processing? Are there tools or methods to directly monitor the sample values at the output of the ADC in the USRP (before digital filtering) to prevent saturation?
Do you have any advice for implementing an automatic gain controller (AGC) based on reliable saturation indicators?
We would appreciate any suggestions or experiences in resolving this issue. If you have encountered a similar problem or have ideas on how to address it, we would be happy to hear your recommendations.
Thank you very much for your help!
On 18/10/2024 11:35, je.amghar@gmail.com wrote:
Hello,
I am currently facing an issue with ADC saturation on a USRP X310
equipped with a UBX daughterboard. We are conducting measurements
using an LTE signal and a sinusoidal input signal, but it seems that
the ADC is saturating, leading to a loss of dynamic range in our
measurements.
Test context:
We are transmitting (using a generator) an LTE signal with a power of
-50 dBm at a center frequency of 1815 MHz. Then, we add a sinusoidal
signal at 1865 MHz with a power of -30 dBm. This second, more powerful
signal seems to be causing the ADC to saturate, even though we don’t
see it directly in the IQ samples due to the digital filtering applied
downstream.
Problem:
We suspect that the ADC saturation occurs before IQ conversion and is
therefore masked by the digital filters. This results in a loss of
dynamic range in our measurements, and we feel that adjusting the gain
based on the IQ samples may not be reliable.
Question:
How can this ADC saturation be detected upstream of the IQ processing?
Are there tools or methods to directly monitor the sample values at
the output of the ADC in the USRP (before digital filtering) to
prevent saturation?
Do you have any advice for implementing an automatic gain controller
(AGC) based on reliable saturation indicators?
We would appreciate any suggestions or experiences in resolving this
issue. If you have encountered a similar problem or have ideas on how
to address it, we would be happy to hear your recommendations.
Thank you very much for your help!
A -30dBm signal applied at the antenna inputs, and then amplified
greatly by the amplifier/mixer/gain-chain ahead of the ADC
would very-likely saturate the ADC. A -30dBm signal from an "over
the air" antenna is one that is thunderingly loud in
the real world. It would not surprise me to find that gain elements
ahead of the ADC are also becoming non-linear.
Turn your gain down.
Dear Marcus,
thank you for your answer. Just to clarify the problem a little better.
We use a UBX160 daughter card.
To have optimal SNR, an automatic gain control has been implemented based on the max IQ value.
The sample rate is 30.72 for LTE decoding.
Unfortunately, high power exists outside our useful band (30.72 MHz) but inside the bandwidth of the 160 daughter card (sampled by the 200 MHz ADC).
We expected the AGC to saturate... but after DSP filtering process by the motherboard, the IQ samples got with UHD is no longer saturated.
As a result, the IQ max is low enough and AGC control continue to increase the gain :-(
It is my current understanding of the situation.
Is there any way to have an estimate of the raw AGC input level when the sample rate is not 200 MHz?
I hope to be clear enough... but surelty not crystal clear :-)
Best regards
Patrice
De: "Marcus D. Leech" patchvonbraun@gmail.com
À: "usrp-users" usrp-users@lists.ettus.com
Envoyé: Vendredi 18 Octobre 2024 17:38:43
Objet: [USRP-users] Re: ADC saturation problem in USRP X310
On 18/10/2024 11:35, je.amghar@gmail.com wrote:
Hello,
I am currently facing an issue with ADC saturation on a USRP X310
equipped with a UBX daughterboard. We are conducting measurements
using an LTE signal and a sinusoidal input signal, but it seems that
the ADC is saturating, leading to a loss of dynamic range in our
measurements.
Test context:
We are transmitting (using a generator) an LTE signal with a power of
-50 dBm at a center frequency of 1815 MHz. Then, we add a sinusoidal
signal at 1865 MHz with a power of -30 dBm. This second, more powerful
signal seems to be causing the ADC to saturate, even though we don’t
see it directly in the IQ samples due to the digital filtering applied
downstream.
Problem:
We suspect that the ADC saturation occurs before IQ conversion and is
therefore masked by the digital filters. This results in a loss of
dynamic range in our measurements, and we feel that adjusting the gain
based on the IQ samples may not be reliable.
Question:
How can this ADC saturation be detected upstream of the IQ processing?
Are there tools or methods to directly monitor the sample values at
the output of the ADC in the USRP (before digital filtering) to
prevent saturation?
Do you have any advice for implementing an automatic gain controller
(AGC) based on reliable saturation indicators?
We would appreciate any suggestions or experiences in resolving this
issue. If you have encountered a similar problem or have ideas on how
to address it, we would be happy to hear your recommendations.
Thank you very much for your help!
A -30dBm signal applied at the antenna inputs, and then amplified
greatly by the amplifier/mixer/gain-chain ahead of the ADC
would very-likely saturate the ADC. A -30dBm signal from an "over
the air" antenna is one that is thunderingly loud in
the real world. It would not surprise me to find that gain elements
ahead of the ADC are also becoming non-linear.
Turn your gain down.
USRP-users mailing list -- usrp-users@lists.ettus.com
To unsubscribe send an email to usrp-users-leave@lists.ettus.com
Your options are to sample at 184.32 MHz and decimate in the host machine
down to 30.72 MHz for LTE decoding, or if that isn't an option then you
need to place an RFNoC block at the output of the radio but before the DDC
which will give you an input power estimate that you can read from the host
periodically. You need to feed that into your AGC algorithm as another
input.
Note the block can just update an internal register that you poll and not
produce any samples.
Brian
On Fri, Oct 18, 2024 at 11:57 AM Patrice PAJUSCO <
patrice.pajusco@imt-atlantique.fr> wrote:
Dear Marcus,
thank you for your answer. Just to clarify the problem a little better.
We use a UBX160 daughter card.
To have optimal SNR, an automatic gain control has been implemented based
on the max IQ value.
The sample rate is 30.72 for LTE decoding.
Unfortunately, high power exists outside our useful band (30.72 MHz) but
inside the bandwidth of the 160 daughter card (sampled by the 200 MHz ADC).
We expected the AGC to saturate... but after DSP filtering process by the
motherboard, the IQ samples got with UHD is no longer saturated.
As a result, the IQ max is low enough and AGC control continue to increase
the gain :-(
It is my current understanding of the situation.
Is there any way to have an estimate of the raw AGC input level when the
sample rate is not 200 MHz?
I hope to be clear enough... but surelty not crystal clear :-)
Best regards
Patrice
*De: *"Marcus D. Leech" patchvonbraun@gmail.com
*À: *"usrp-users" usrp-users@lists.ettus.com
*Envoyé: *Vendredi 18 Octobre 2024 17:38:43
*Objet: *[USRP-users] Re: ADC saturation problem in USRP X310
On 18/10/2024 11:35, je.amghar@gmail.com wrote:
Hello,
I am currently facing an issue with ADC saturation on a USRP X310
equipped with a UBX daughterboard. We are conducting measurements
using an LTE signal and a sinusoidal input signal, but it seems that
the ADC is saturating, leading to a loss of dynamic range in our
measurements.
Test context:
We are transmitting (using a generator) an LTE signal with a power of
-50 dBm at a center frequency of 1815 MHz. Then, we add a sinusoidal
signal at 1865 MHz with a power of -30 dBm. This second, more powerful
signal seems to be causing the ADC to saturate, even though we don’t
see it directly in the IQ samples due to the digital filtering applied
downstream.
Problem:
We suspect that the ADC saturation occurs before IQ conversion and is
therefore masked by the digital filters. This results in a loss of
dynamic range in our measurements, and we feel that adjusting the gain
based on the IQ samples may not be reliable.
Question:
How can this ADC saturation be detected upstream of the IQ processing?
Are there tools or methods to directly monitor the sample values at
the output of the ADC in the USRP (before digital filtering) to
prevent saturation?
Do you have any advice for implementing an automatic gain controller
(AGC) based on reliable saturation indicators?
We would appreciate any suggestions or experiences in resolving this
issue. If you have encountered a similar problem or have ideas on how
to address it, we would be happy to hear your recommendations.
Thank you very much for your help!
A -30dBm signal applied at the antenna inputs, and then amplified
greatly by the amplifier/mixer/gain-chain ahead of the ADC
would very-likely saturate the ADC. A -30dBm signal from an "over
the air" antenna is one that is thunderingly loud in
the real world. It would not surprise me to find that gain elements
ahead of the ADC are also becoming non-linear.
Turn your gain down.
USRP-users mailing list -- usrp-users@lists.ettus.com
To unsubscribe send an email to usrp-users-leave@lists.ettus.com
USRP-users mailing list -- usrp-users@lists.ettus.com
To unsubscribe send an email to usrp-users-leave@lists.ettus.com
On 18/10/2024 12:06, Brian Padalino wrote:
Your options are to sample at 184.32 MHz and decimate in the host
machine down to 30.72 MHz for LTE decoding, or if that isn't an option
then you need to place an RFNoC block at the output of the radio but
before the DDC which will give you an input power estimate that you
can read from the host periodically. You need to feed that into your
AGC algorithm as another input.
Note the block can just update an internal register that you poll and
not produce any samples.
Brian
Without knowing much about LTE DSP and DR requirements, once your gain
level is at a level where you have adequate SNR in most
cases, then the only thing remaining is if your downstream DSP
algorithms require that samples be in the "saturated" {-1,+1}
domain, that can be done DSP-wise without ever touching the RF gain.
On Fri, Oct 18, 2024 at 11:57 AM Patrice PAJUSCO
patrice.pajusco@imt-atlantique.fr wrote:
Dear Marcus,
thank you for your answer. Just to clarify the problem a little
better.
We use a UBX160 daughter card.
To have optimal SNR, an automatic gain control has been
implemented based on the max IQ value.
The sample rate is 30.72 for LTE decoding.
Unfortunately, high power exists outside our useful band (30.72
MHz) but inside the bandwidth of the 160 daughter card (sampled by
the 200 MHz ADC).
We expected the AGC to saturate... but after DSP filtering process
by the motherboard, the IQ samples got with UHD is no longer
saturated.
As a result, the IQ max is low enough and AGC control continue to
increase the gain :-(
It is my current understanding of the situation.
Is there any way to have an estimate of the raw AGC input level
when the sample rate is not 200 MHz?
I hope to be clear enough... but surelty not crystal clear :-)
Best regards
Patrice
------------------------------------------------------------------------
*De: *"Marcus D. Leech" <patchvonbraun@gmail.com>
*À: *"usrp-users" <usrp-users@lists.ettus.com>
*Envoyé: *Vendredi 18 Octobre 2024 17:38:43
*Objet: *[USRP-users] Re: ADC saturation problem in USRP X310
On 18/10/2024 11:35, je.amghar@gmail.com wrote:
Hello,
I am currently facing an issue with ADC saturation on a USRP X310
equipped with a UBX daughterboard. We are conducting measurements
using an LTE signal and a sinusoidal input signal, but it seems
that
the ADC is saturating, leading to a loss of dynamic range in our
measurements.
Test context:
We are transmitting (using a generator) an LTE signal with a
power of
-50 dBm at a center frequency of 1815 MHz. Then, we add a
sinusoidal
signal at 1865 MHz with a power of -30 dBm. This second, more
powerful
signal seems to be causing the ADC to saturate, even though we
don’t
see it directly in the IQ samples due to the digital filtering
applied
downstream.
Problem:
We suspect that the ADC saturation occurs before IQ conversion
and is
therefore masked by the digital filters. This results in a loss of
dynamic range in our measurements, and we feel that adjusting
the gain
based on the IQ samples may not be reliable.
Question:
How can this ADC saturation be detected upstream of the IQ
processing?
Are there tools or methods to directly monitor the sample values at
the output of the ADC in the USRP (before digital filtering) to
prevent saturation?
Do you have any advice for implementing an automatic gain
controller
(AGC) based on reliable saturation indicators?
We would appreciate any suggestions or experiences in resolving
this
issue. If you have encountered a similar problem or have ideas
on how
to address it, we would be happy to hear your recommendations.
Thank you very much for your help!
A -30dBm signal applied at the antenna inputs, and then amplified
greatly by the amplifier/mixer/gain-chain ahead of the ADC
would very-likely saturate the ADC. A -30dBm signal from an
"over
the air" antenna is one that is thunderingly loud in
the real world. It would not surprise me to find that gain
elements
ahead of the ADC are *also* becoming non-linear.
Turn your gain down.
_______________________________________________
USRP-users mailing list -- usrp-users@lists.ettus.com
To unsubscribe send an email to usrp-users-leave@lists.ettus.com
_______________________________________________
USRP-users mailing list -- usrp-users@lists.ettus.com
To unsubscribe send an email to usrp-users-leave@lists.ettus.com
Thank you for your feedback and possible tracks.
- yes about decimation in host machine but computation capacity of the host must be checked :-)
- not yet familiar with RFNOC, I will have a look
Signal analysis is done offline, but IQ data are stored continously during the car trip , that is why it is important for us to have a good quality of sampling
De: "Marcus D. Leech" patchvonbraun@gmail.com
À: "Brian Padalino" bpadalino@gmail.com, "Patrice PAJUSCO" patrice.pajusco@imt-atlantique.fr
Cc: "usrp-users" usrp-users@lists.ettus.com
Envoyé: Vendredi 18 Octobre 2024 18:13:57
Objet: Re: [USRP-users] Re: ADC saturation problem in USRP X310
On 18/10/2024 12:06, Brian Padalino wrote:
Your options are to sample at 184.32 MHz and decimate in the host machine down to 30.72 MHz for LTE decoding, or if that isn't an option then you need to place an RFNoC block at the output of the radio but before the DDC which will give you an input power estimate that you can read from the host periodically. You need to feed that into your AGC algorithm as another input.
Note the block can just update an internal register that you poll and not produce any samples.
Brian
Without knowing much about LTE DSP and DR requirements, once your gain level is at a level where you have adequate SNR in most
cases, then the only thing remaining is if your downstream DSP algorithms require that samples be in the "saturated" {-1,+1}
domain, that can be done DSP-wise without ever touching the RF gain.
BQ_BEGIN
On Fri, Oct 18, 2024 at 11:57 AM Patrice PAJUSCO < [ mailto:patrice.pajusco@imt-atlantique.fr | patrice.pajusco@imt-atlantique.fr ] > wrote:
BQ_BEGIN
Dear Marcus,
thank you for your answer. Just to clarify the problem a little better.
We use a UBX160 daughter card.
To have optimal SNR, an automatic gain control has been implemented based on the max IQ value.
The sample rate is 30.72 for LTE decoding.
Unfortunately, high power exists outside our useful band (30.72 MHz) but inside the bandwidth of the 160 daughter card (sampled by the 200 MHz ADC).
We expected the AGC to saturate... but after DSP filtering process by the motherboard, the IQ samples got with UHD is no longer saturated.
As a result, the IQ max is low enough and AGC control continue to increase the gain :-(
It is my current understanding of the situation.
Is there any way to have an estimate of the raw AGC input level when the sample rate is not 200 MHz?
I hope to be clear enough... but surelty not crystal clear :-)
Best regards
Patrice
De: "Marcus D. Leech" < [ mailto:patchvonbraun@gmail.com | patchvonbraun@gmail.com ] >
À: "usrp-users" < [ mailto:usrp-users@lists.ettus.com | usrp-users@lists.ettus.com ] >
Envoyé: Vendredi 18 Octobre 2024 17:38:43
Objet: [USRP-users] Re: ADC saturation problem in USRP X310
On 18/10/2024 11:35, [ mailto:je.amghar@gmail.com | je.amghar@gmail.com ] wrote:
Hello,
I am currently facing an issue with ADC saturation on a USRP X310
equipped with a UBX daughterboard. We are conducting measurements
using an LTE signal and a sinusoidal input signal, but it seems that
the ADC is saturating, leading to a loss of dynamic range in our
measurements.
Test context:
We are transmitting (using a generator) an LTE signal with a power of
-50 dBm at a center frequency of 1815 MHz. Then, we add a sinusoidal
signal at 1865 MHz with a power of -30 dBm. This second, more powerful
signal seems to be causing the ADC to saturate, even though we don’t
see it directly in the IQ samples due to the digital filtering applied
downstream.
Problem:
We suspect that the ADC saturation occurs before IQ conversion and is
therefore masked by the digital filters. This results in a loss of
dynamic range in our measurements, and we feel that adjusting the gain
based on the IQ samples may not be reliable.
Question:
How can this ADC saturation be detected upstream of the IQ processing?
Are there tools or methods to directly monitor the sample values at
the output of the ADC in the USRP (before digital filtering) to
prevent saturation?
Do you have any advice for implementing an automatic gain controller
(AGC) based on reliable saturation indicators?
We would appreciate any suggestions or experiences in resolving this
issue. If you have encountered a similar problem or have ideas on how
to address it, we would be happy to hear your recommendations.
Thank you very much for your help!
A -30dBm signal applied at the antenna inputs, and then amplified
greatly by the amplifier/mixer/gain-chain ahead of the ADC
would very-likely saturate the ADC. A -30dBm signal from an "over
the air" antenna is one that is thunderingly loud in
the real world. It would not surprise me to find that gain elements
ahead of the ADC are also becoming non-linear.
Turn your gain down.
USRP-users mailing list -- [ mailto:usrp-users@lists.ettus.com | usrp-users@lists.ettus.com ]
To unsubscribe send an email to [ mailto:usrp-users-leave@lists.ettus.com | usrp-users-leave@lists.ettus.com ]
USRP-users mailing list -- [ mailto:usrp-users@lists.ettus.com | usrp-users@lists.ettus.com ]
To unsubscribe send an email to [ mailto:usrp-users-leave@lists.ettus.com | usrp-users-leave@lists.ettus.com ]
BQ_END
BQ_END
If your input power doesn't vary a lot, and you can simply find a good gain
point that doesn't saturate any AGCs, then no RFNoC is required. That's
probably the easiest way. Adding an RFNoC block is not easy if you're doing
it for the first time, and you need some FPGA development experience. Of
course, if you do go down that route and have questions then let us know!
--M