Discussion and technical support related to USRP, UHD, RFNoC
View all threadsHi Everyone,
The header of my N300 yaml file is shown below, but this results in an HG
image being built, not the XG. (I am building this with UHD-4.8.)
The HG image does contain my new RFNoC block, with the right endpoints etc.,
so I believe the yaml config should be (mostly) correct?
I find it strange because the bit file that is generated also has the name
"usrp_n300_fpga_XG.bit".
When loaded, "usrp_find_devices" returns:
Device Address:
serial: XXXXXXX
claimed: False
fpga: HG
mgmt_addr: 127.0.0.1
name: ni-n3xx-XXXXXXX
product: n300
type: n3xx
Is there something I might be missing somewhere?
Many thanks, Kevin
schema: rfnoc_imagebuilder_args # Identifier for the schema used to
validate this file
copyright: >- # Copyright information used in file
headers
Copyright 2023 Ettus Research, a National Instruments Brand
license: >- # License information used in file
headers
SPDX-License-Identifier: LGPL-3.0-or-later
version: '1.0' # File version
chdr_width: 64 # Bit width of the CHDR bus for this
image
device: 'n300'
default_target: 'N300_XG'
image_core_name: 'usrp_n300_fpga_XG'
Hi Kevin,
confirm this is a bug. You can force the correct target by specifying
rfnoc_image_builder -t N310_XG [...your other arguments...]
...which we confirm works. We'll have a fix for this on the way.
--M
On Wed, Feb 12, 2025 at 9:26 AM Kevin Williams kevin.williams@vastech.co.za
wrote:
Hi Everyone,
The header of my N300 yaml file is shown below, but this results in an HG
image being built, not the XG. (I am building this with UHD-4.8.)
The HG image does contain my new RFNoC block, with the right endpoints
etc.,
so I believe the yaml config should be (mostly) correct?
I find it strange because the bit file that is generated also has the name
"usrp_n300_fpga_XG.bit".
When loaded, "usrp_find_devices" returns:
Device Address:
serial: XXXXXXX
claimed: False
fpga: HG
mgmt_addr: 127.0.0.1
name: ni-n3xx-XXXXXXX
product: n300
type: n3xx
Is there something I might be missing somewhere?
Many thanks, Kevin
schema: rfnoc_imagebuilder_args # Identifier for the schema used to
validate this file
copyright: >- # Copyright information used in
file
headers
Copyright 2023 Ettus Research, a National Instruments Brand
license: >- # License information used in file
headers
SPDX-License-Identifier: LGPL-3.0-or-later
version: '1.0' # File version
chdr_width: 64 # Bit width of the CHDR bus for
this
image
device: 'n300'
default_target: 'N300_XG'
image_core_name: 'usrp_n300_fpga_XG'
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Thanks Martin!
From: Martin Braun martin.braun@ettus.com
Sent: Wednesday, 12 February 2025 15:38
Cc: usrp-users@lists.ettus.com
Subject: [EXTERNAL][USRP-users] Re: N300 HG image being built instead of XG
Hi Kevin,
confirm this is a bug. You can force the correct target by specifying
rfnoc_image_builder -t N310_XG [...your other arguments...]
...which we confirm works. We'll have a fix for this on the way.
--M
On Wed, Feb 12, 2025 at 9:26 AM Kevin Williams <kevin.williams@vastech.co.za mailto:kevin.williams@vastech.co.za > wrote:
Hi Everyone,
The header of my N300 yaml file is shown below, but this results in an HG
image being built, not the XG. (I am building this with UHD-4.8.)
The HG image does contain my new RFNoC block, with the right endpoints etc.,
so I believe the yaml config should be (mostly) correct?
I find it strange because the bit file that is generated also has the name
"usrp_n300_fpga_XG.bit".
When loaded, "usrp_find_devices" returns:
Device Address:
serial: XXXXXXX
claimed: False
fpga: HG
mgmt_addr: 127.0.0.1 https://url.za.m.mimecastprotect.com/s/Y5OZCj2MKKfRD64sWfBTmV7Tn?domain=127.0.0.1
name: ni-n3xx-XXXXXXX
product: n300
type: n3xx
Is there something I might be missing somewhere?
Many thanks, Kevin
schema: rfnoc_imagebuilder_args # Identifier for the schema used to
validate this file
copyright: >- # Copyright information used in file
headers
Copyright 2023 Ettus Research, a National Instruments Brand
license: >- # License information used in file
headers
SPDX-License-Identifier: LGPL-3.0-or-later
version: '1.0' # File version
chdr_width: 64 # Bit width of the CHDR bus for this
image
device: 'n300'
default_target: 'N300_XG'
image_core_name: 'usrp_n300_fpga_XG'
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