pablo alvarez wrote:

I presume you mean low pass filtering the pulse train whose width is
equal to the input to output delay of a synchroniser.
The dc level depends on the trigger frequency as well as the
synchroniser delay.

Pablo

1. The HP5359A (and the 5370A/B) used a phase locked startable oscillator.
   The classic gated oscillator uses a delay line to determine the
   oscillator frequency.
   These are commercially available or you can build your own using an
   inverting gate and a length of coax or other delay line for higher
   performance.

2. The ACAM TDC-GPX has linearity errors much larger than 10ps for short
   time intervals (< 120ns).
   However if the time interval can be guaranteed to exceed some minimum
   (120ns) an integral non linearity of around 10ps is possible.
   For longer time intervals the measurement jitter will be significant at
   the 10ps level.
   The ACAM TDC-GPX has an internal delay locked loop option that allows
   the internal delay step size to be locked to an external reference
   frequency.

Another delay technique is to use a tapped chain of gates in an FPGA can
be used to implement a fine delay.
A DLL can be used to stabilise the delays.

Another option is to use a pair of ADCs to simultaneously sample a
quadrature pair of 10MHz sinewaves.
Together with a dual phase synchroniser to sample a counter clocked at
10MHz, a resolution on the order of 10ps or so is possible with a range
limited by the counter length.
An LTC1407A-1 dual simultaneous sampling ADC allows sample rates up to
1.5MHz with adequate linearity if driven differentially.
However an inverse tangent calculation is required for each measurement

• this could easily be done in an FPGA within a few tens of nanosec.

To avoid using a fine delay with a large range using a higher frequency
(eg 40MHz or higher) local clock phase locked to 10MHz will reduce the
required fine delay range significantly.

Bruce

pablo alvarez wrote:

Pablo

Surely it would be better to sampled the low pass filtered latched
trigger transition with a pipeline ADC clocked at 100MHz or more.
The threshold crossing time of the ADC input can then be calculated from
the ADC samples (using WSK interpolation etc) provided there are
sufficient samples taken during the transition.
The low pass filter delay will have to be taken into account in
determining the actual time of occurrence of the trigger input signal.
A long tailed pair with a differential output could be used to drive a
differential low pass filter connected to the differential ADC input.
A resolution of 10ps or better should be achievable with the offset
stability largely determined by the analog filter delay instability (due
to time, temperature etc).
The slope should be very stable as it is largely determined by the ADC
clock and ADC linearity.

Bruce

I meant to say that using a higher resolution pipeline ADC than the
AD9626 may be better as the SNR limits the AD9626 to about 10.5 bits at
low input frequencies.
This means that the equivalent timing noise will be around 14ps if the
ADC input has a 10ns transition time and the ADC is clocked at 250MHz.
An ADC with 14 effective bit performance with a 100MHz sampling clock
should have an equivalent timing noise of around 5ps or so when the ADC
input has a 25nS transition time.
An AD9446 should achieve a timing noise level of around 7ps rms or so
when clocked at 100MHz.

A pulse centroid timing technique using an ADC to sample a quasi
Gaussian pulse has been demonstrated to have a stability of 10-20ps or
so after calibration.
A timing technique using WSK interpolation should have somewhat greater
stability as the analog signal processing required is much simpler.

Bruce

Bruce Griffiths bruce.griffiths@xtra.co.nz wrote:

Arctan is the mathematical solution, but by using some extra knowledge
(that the amplitude of both sin and cos can be measured
but are not necessarily exactly equal to the level of DAC resolution) and the
common sense that at some parts of the cycle, cos is changing very slowly
and sin is changing very rapidly, or the other way around, resolution
can be substantially improved (nearly a factor of two).

Giving the slowly changing phase the same weight in the calculation
as the rapidly changing phase is unwise. It is wise to calibrate
the amplitudes and relative phases of sin and cos generators using
the same DAC's as you're going to use to do the measurement.

We were doing all this 30 years ago using CAMAC crates and PDP-8's,
no FPGA for arctan but we spent a good amount of effort in
weighting the calculation to extract
every bit of time resolution given our relatively coarse DAC resolution.

Much of this is in the 1940's Radiation Lab series, there
are extensive sections on sin/cos wave generation, and they
do note when doing the time measurment that you want to move
the trace so you are using the rapidly changing phase.
Of course they weren't necessarily using 10MHz sin/cos generators
back then, mostly they were using custom-wound nonlinear wire-wound pots
and motors driving shafts to make the phases :-).

Tim.

Thanks Tim and Bruce for your info! It is precious.

By the way you will have all the schematics and sources will be on the
web. I will keep you informed.

Perhaps the MC100EP196B could be useful an oscillator here. I could
set a total delay of 10ns and try use the analog control input to tune
the period. The phase could be measured with an extra TIM.

I have thought many times of implementing such a tapped delay line but
always left it for another moment. It is just a bit anoying that ones
has to fix the placement of the taps. On the other hand one could just
let the router place your design and use later statistical code
coverage to calibrate the design at startup.  It may be interesting
replicating the tapped delay lines. The resulting scale would be the
intersection of the original codes.

I have seen the paper you are refering to in your site. This method is
not as easy as it seems at the end. You need to generate a perfect
200MHz sine and cosine. You need to monitor its amplitude and to
obtain the maximum performance you need to have a good picture of the
nonlinarities of both sine and cosine. Finally the  LTC1407A-1 latency
is similar to that of the  AD9626.

Certainly, I will try use a clock as fast as possible.

Thanks for suggesting the AD9446  and the WSK interpolation. I had
thought of  keeping a normalized waveform of the pulse rising edge
stored in a RAM. By normalized I mean doing the starting points equal
to -.5 and the final points equal to 0.5. I can try to autogenerate
this waveform using a fine delay line and later use statistical code
coverage to do a fine calibration.
By the way I do not understand very well how do you use WSK
interpolation. Normally you use it to find the amplitude level between
two samples, but here we are trying to solve the inverse problem. We
need to know at which moment the signal passed over a given threshold.
How do you solve it?

Pablo

pablo alvarez wrote:

A delay line oscillator should have lower noise.
A varicap can be used to adjust the delay line oscillator frequency
slightly as in the 530A/B or 5359A vernier oscillators.

A pair of 10MHz sine and quadrature waveforms will suffice for 10ps
resolution when using an LTC1407A-1.
If the sine and cosine signal amplitudes track slow variations cancel
when using the ratio of the sine and cosine samples.
Calibration could be done by using a suitable input frequency like
17.3447MHz divided by 35 to sample the sine and cosine signals.
Successive samples should then sample the quadrature pair at different
phases allowing measurement of effective gain differences, effective
phase offset between channels, and harmonic amplitudes.

Pablo

One can use iteration to find the threshold crossing, just as one does
in finding the roots of a polynomial or other function.
WSK interpolation (with a suitable window function) allows one to
calculate the value of the signal at each intermediate point between
samples required by the iteration algorithm (Newton Raphson, binary
search etc).
When one obtains a pair of interpolated points that are sufficiently
close to each other and preferably straddling the threshold crossing
linear interpolation will suffice for the final estimate.
One advantage of this technique is that a model of the signal waveform
isn't required.
The threshold could also be defined as say the average of the 0 and 1
levels as measured by the ADC remote from the transition.
This should significantly reduce the effect of offset and gain variations.

Bruce