[CITASA] Contents of IJERTCS inaugural issue, Vol 1 Issue 1
The contents of the latest issue of:
International Journal of Embedded and Real-Time Communication Systems (IJERTCS)
Official Publication of the Information Resources Management Association
Volume 1, Issue 1, January-March 2010
Published: Quarterly in Print and Electronically
ISSN: 1947-3176 EISSN: 1947-3184
Published by IGI Publishing, Hershey-New York, USA
Editor-in-Chief: Seppo Virtanen, University of Turku, Finland
EDITORIAL PREFACE
Seppo Virtanen, University of Turku, Finland
To read the preface, click on the link below.
http://www.igi-global.com/Files/Ancillary/jertcs.2010.1.1-Preface.pdf
PAPER ONE
Current Challenges in Embedded Communication Systems
Jouni Isoaho, University of Turku, Finland
Seppo Virtanen, University of Turku, Finland
Juha Plosila, University of Turku, Finland
This article defines and analyses key challenges met in future embedded systems in networked multimedia and communication applications. Self-awareness, interoperability and embedded security are used to characterize different aspects of designing and implementing next generation embedded systems. The dynamic nature of applications and implementations as well as possible technological faults and variations need to be considered in system verification and modeling. A new design layer needs to be added to current NoC platforms in order to build procedures that take into account dynamic system reconfigurations, fault-tolerance aspects and flexible portability. Increased modularity and networked implementations create a need for trust management mechanisms between system components and technology for analyzing validity and correctness of received application and system configuration information.
To obtain a copy of the entire article, click on the link below.
http://www.igi-global.com/Bookstore/Article.aspx?TitleId=40930
PAPER TWO
Embedded Networks in Mobile Devices
Sergey Balandin, Nokia Research Center, Finland
Michel Gillet, Nokia Devices, Finland
The concept of a mobile phone has recently transformed into a new concept of mobile multimedia devices capable of performing multiple complex tasks and integrating multiple functionalities. It has resulted in a significant increase of device integration costs and complicated deployment of new technologies. Device integrator companies favor modularity everywhere possible, which results in a new trend toward networked architectures for the mobile devices. However, comparing to the best-known embedded network solutions, e.g., SoC and NoC, these architectures have unique constraints and requirements, which also are significantly different from the wide area networks. The main constraints are power consumption and having a modular architecture to allow reuse of the components. Transition to the new architectures for mobile devices is a time consuming task that requires the analysis of many solutions applied in other contexts, especially for embedded protocols, QoS and resource management. This article reviews the state of the art in embedded networks research and the key assumptions, restrictions and limitations faced by designers of embedded networks architectures for mobile devices.
To obtain a copy of the entire article, click on the link below.
http://www.igi-global.com/Bookstore/Article.aspx?TitleId=40931
PAPER THREE
Generating Process Network Communication Infrastructure for Custom Multi-Core Platforms
Peter Sørensen (Technical University of Denmark, Denmark)
Jan Madsen (Technical University of Denmark, Denmark)
We present an approach for generating implementations of abstraction layers implementing the communication infrastructure of applications modeled as process networks. Our approach is unique in that it does not rely on assumptions about the capabilities and topology of the underlying platform. Instead, a generic implementation is adapted to the particular platform based on information retrieved from analyzing the platform. At the heart of the approach is a novel method for analyzing the capabilities of custom execution platforms composed of components. The versatility and usefulness of the approach and analysis method is demonstrated through a case study.
To obtain a copy of the entire article, click on the link below.
http://www.igi-global.com/Bookstore/Article.aspx?TitleId=40932
PAPER FOUR
Parallel Programming and Its Architectures Based on Data Access Separated Algorithm Kernels
Dake Liu, Linköping University, Sweden
Joar Sohl, Linköping University, Sweden
Jian Wang, Linköping University, Sweden
A novel master-multi-SIMD architecture and its kernel (template) based parallel programming flow is introduced as a parallel signal processing platform. The name of the platform is ePUMA (embedded Parallel DSP processor architecture with Unique Memory Access). The essential technology is to separate data accessing kernels from arithmetic computing kernels so that the run-time cost of data access can be minimized by running it in parallel with algorithm computing. The SIMD memory subsystem architecture based on the proposed flow dramatically improves the total computing performance. The hardware system and programming flow introduced in this article will primarily aim at low-power high-performance embedded parallel computing with low silicon cost for communications and similar real-time signal processing.
To obtain a copy of the entire article, click on the link below.
http://www.igi-global.com/Bookstore/Article.aspx?TitleId=40933
PAPER FIVE
Joint Validation of Application Models and Multi-Abstraction Network-on-Chip Platforms
Sanna Määttä, Tampere University of Technology, Finland
Leandro Möller, Technische Universität Darmstadt, Germany
Leandro Indrusiak, University of York, UK
Luciano Ost, Catholic University of Rio Grande do Sul, Brazil
Manfred Glesner, Technische Universität Darmstadt, Germany
Jari Nurmi, Tampere University of Technology, Finland
Fernando Moraes, Catholic University of Rio Grande do Sul, Brazil
Application models are often disregarded during the design of multiprocessor Systems-on-Chip (MPSoC). This is due to the difficulties of capturing the application constraints and applying them to the design space exploration of the platform. In this article we propose an application modelling formalism that supports joint validation of application and platform models. To support designers on the trade-off analysis between accuracy, observability, and validation speed, we show that this approach can handle the successive refinement of platform models at multiple abstraction levels. A case study of the joint validation of a single application successively mapped onto three different platform models demonstrates the applicability of the presented approach.
To obtain a copy of the entire article, click on the link below.
http://www.igi-global.com/Bookstore/Article.aspx?TitleId=40934
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For full copies of the above articles, check for this issue of the International Journal of Embedded and Real-Time Communication Systems (IJERTCS)
(IJERTCS) in your institution's library. This journal is also included in the IGI Global aggregated “InfoSci-Journals” database: www.infosci-journals.com.
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CALL FOR PAPERS
Mission of IJERTCS:
The mission of the **International Journal of Embedded and Real-Time Communication Systems (IJERTCS)**is to disseminate recent advancements and innovations in this interdisciplinary research area for field researchers, practitioners, scientists, academicians, students, and IT professionals. IJERTCS focuses on overcoming challenges involved in the rapid development of embedded communication systems towards feature-rich multimedia computers.
Coverage of IJERTCS:
Asynchronous and synchronous circuit techniques
Design methods
Embedded networks (built-in networks in embedded communication devices)
Emerging new topics
Fault-tolerant hardware and software technologies
Formal design and verification methods
Hardware and software solutions for protocol processing
Hardware and software solutions for real-time systems
Hardware platforms and technologies
Hardware/software co-design
Modeling and verification methods
On-chip communication in SoC and NoC
OWA (open wireless architecture)
Performance modeling
Platform based design
Real-time computing
Reconfigurable systems
Security issues and technologies
Single-chip SDR (software defined radio) solutions
Software design
Testing techniques
Interested authors should consult the journal's manuscript submission guidelines at www.igi-global.com/ijertcs
All inquiries and submissions should be sent to:
Editor-in-Chief: Seppo Virtanen at seppo.virtanen@utu.fi