michael taylor wrote:

Michael

The analog circuitry for a sigma-delta DAC is attached.
The input is optically isolated using a high speed low jitter CMOS
optocoupler (Avago produce an equivalent device) to break low frequency
ground loops.
Similarly an RF transformer should be used to couple the OCXO output to
the Digital board breaking another potential low frequency ground loop.
The task of the microprocessor firmware is to generate the delta sigma 1
bit input data for the optocoupler.

Alternatively one of Analog devices chip scale transformer isolators
could be used.

Bruce

Bruce Griffiths wrote:

Michael

Attached is the circuit for a 1 bit phase detector.
HCMOS should be perfectly adequate given that the flipflop is allowed
several hundred millisec to settle before being read by the microprocessor.
An RF transformer isolated clock shaper should be used to shape the OCXO
output and avoid low frequency ground loops.
You probably want at least a 2 output distribution amplifier (unless
your OCXO has multiple isolated outputs eg FTS1200 OSA8607, some of the
Wenzel OCXOs, etc.) to allow the OCXO output to be used for other
applications as well.

The position of the divider output transition is adjusted by the control
algorithm with respect to the leading edge of the PPS signal so that the
D flipflop Q has a 50% chance of being 1 when read by the
microprocessor. The effective resolution is determined by the jitter of
the leading edge of the PPS pulse.

Bruce

Hi Bruce,

Fine, you don't like the words "far better performance"... okay ;-)
you do recognize the small advantage in noise but
gave no relevance to the other aspects namely the
lock acquisition, the fact that I can monitor the jitter over time
etc. (all of them were contained in my word "performance"
not just the noise).

you wrote,

Humm?! I did tried them, that's exactly what I said !!!
Note that I do have the hardware on a CPLD so schemes
can be done on type-compile-and-test basis without
soldering wires hi ;-)

Geeee, using a CPLD does not add complexity, it is just one chip
and it offers the commodity of being easily configured etc.
Also the power consumption is surely not an issue, if you
are not happy with the 50 to 100mA you may draw from 3.3v
just use a low power CPLD (like tha maxIIZ) and get
only 10 to 20mA.

On the comments about the filter and bandwidth I do agree
with you it would be good to have most of it digital
(doesn't need to be necessarily on a CPU... inside the CPLD
is the same) I do have versions with integration also
in digital and I'm still in the process of improving it.
I believe I may get rid off of some of the inconvenient
analog filtering, in the next VHDL iterations hi ;-)

One thing is puzzling me, if you suggest using a
single D flip-flop and want it simple as you say
I presume you have also to filter in analog ?!
So you end up with a slightly worst phase comparator
and the less convenient analog filter :-(

Or do you need to add a microcontroller and a DAC ?
If that is the case, there goes off your complexity issue
much higher than a simple CPLD.

Luis Cupido.
ct1dmk

Luis Cupido wrote:

Its not too difficult to add a couple of extra flipflops plus associated
delays to allow reasonably accurate estimation of noise if thats useful.

A theoretical understanding the performance tradeoffs can save a lot of
time and effort.

You have to keep in mind that not everyone on this list can or wants to
program a CPLD.

Where did you get that from??
No analog filtering of the D flipflop output is required.

Try reading up on how the radio astronomers digitise their noise like
signals.
You should also look at why a 1-2 bit ADC suffices for most GPS timing
receivers.

I've used plenty of CPLDs but see no reason to use one when it isnt
necessary.
If you want really high phase measurement resolution then the high noise
internal environment of a CPLD can add plenty of jitter and unwanted
crosstalk.
You are unlikely to ever achieve a jitter of 10picosec or less with a
standard CPLD whereas this is readily achieved using a single flipflop
or a wideband ADC used as a phase detector.

Bruce

Bruce,

The sentence in my perspective sounds a bit like this:
I've used plenty of TTL and CMOS but see no reason to use them
when I could fit them all on a CPLD.

I do understand that some may not want to get into this kind of
devices, however I see not much of a difference of
learning you way with microcontrollers, CPLDs or with any
digital IC's these days.

CPLDs in general do bring simplicity but do require learning
how to use them and for various reasons that may be undesirable
and be confused with a complexity issue while it is just a learning
issue.
Very good, I do respect the usage of a bunch of CMOS/TTL chips if
someone doesn't want to spend the
effort of learning how to use a CPLD. When it comes to use CPUs for
tasks better done by straight logic (and there are many examples
out there) then I think it is not the right option.
All understood so let's not discuss that any further.

Now you got me lost.

We were talking about a GPSDO, that is locking
an VCXO on the GPS time (1pps or else)
So by the end of it you need an analog
signal to control the voltage input of the VCXO. Right ?

Where you get that from ?
If not by filtering your flip-flop output
what else you have in between the 1pps and the VCXO ?
CPU's DAC's ????
if so how does your complexity arguments still apply ?

Luis Cupido

On Dec 12, 2007 7:33 AM, Luis Cupido cupido@mail.ua.pt wrote:

Bruce also alludes to the higher jitters of CPLD versus Advanced/High
Speed CMOS logic gates (AC or HC families).

This has to do with the programmable nature of CPLD / FPGA ICs as I
understand it.
Ref: http://www.febo.com/pipermail/time-nuts/2007-April/025299.html

-Michael

Bruce Griffiths wrote:

Yes!  I now feel inspired to go spin a design after studying all of
these messages in this
thread.  My only constraint is that the parts have to pass the "Digikey"
test, i.e. I have to
be able to order small quantities from Digikey, Mouser, or the like.
It's nearly impossible
for a hobbyist like me to get small quantities of more exotic parts.
The big distributors have
gotten better in the last decade about taking small orders, but still
often have minimum qty/piece
requirements that they won't waive.  Even worse are orderable, but
unobtainable parts -- Maxim
seems to have a huge library of such "virtual" chips that have lead
times of 1/2 year or more.

Scott

Luis Cupido wrote:

Some software, including a sigma delta DAC, the effect of which is no
different, in principle, than the filtering etc required by any of your
phase detector implementations.
The 1 bit phase error samples are processed in software (or hardware
depending on one's inclinations, expertise, etc) in a similar way that
samples from an N (>1) phase detector samples are, to produce a digital
output for a DAC which drives the OCXO EFC input. The only difference is
that a sigma delta DAC is used instead of a conventional DAC.

The interpretation of "complexity " depends on ones background and
experience.
The originator of the thread indicated that they had some microprocessor
software experience.

I was trying to tailor the design to the stated strengths of the
originator of the thread.

If one is trying to "squeeze" the ultimate in performance when using a
GPS receiver to discipline an OCXO, then carrier phase measurements
potentially offer much higher performance than can be achieved by using
the PPS output of a typical GPS timing receiver.
However only a few commercially available GPS receivers are suitable for
this application.
The GPS receiver oscillators all have to be phase locked to the OCXO
being disciplined.
This approach has been used in at least one commercially available GPSDOCXO.
In principle a GPS receiver has all the required measurement hardware,
so all that is required are suitable algorithms implemented in either
software running on a DSP, microprocessor, etc, or implemented in
hardware (CPLD etc).

Bruce

Scott Burris wrote:

Scott

I usually checkout the availability of parts in small quantity from such
sources, although which suppliers to check depends on your location.
Locally RS Components and Farnell are very good (they are also good
sources in Europe). I have a Digikey printed catalog with prices in my
local currency($NZ) (I have ordered a few things from them when I cant
easily get them locally). Linear Technologies on line ordering facility
works well for some of their more exotic parts and evaluation kits.

As far as I know Dallas/Maxim appears to be the only source of suitable
affordable programmable delay chips for this particular application.
In principle one could use a tapped chain of gates in a CPLD, however
continuous calibration of the delay is required (a delay locked loop
controlling the gate propagation delay by adjusting its power supply
voltage to compensate for the effect of temperature variations is one
technique). However unless the Dallas chips become hard to obtain its
probably best to leave this as a backup option.

What processor are you intending to use to decipher the sawtooth
correction messages from the GPS timing receiver?
You could use an inexpensive microprocessor dedicated to this simple task.
Another microprocessor can be used to discipline the OCXO.
Depending on your experience, this can be easier than using a single
microprocessor to do everything.

Bruce