Hello,

I'm new to RFNoC and have been trying to implement the example described in "Getting Started with RFNoC in UHD 4.0." Unfortunately, all my attempts have failed. Here's what I've done so far:

$ cp -r <repo>/host/examples/rfnoc-example ~/
$ mv ~/rfnoc-example ~/rfnoc-demo
$ mkdir ~/rfnoc-demo/build
$ cd ~/rfnoc-demo/build
$ cmake -DUHD_FPGA_DIR=<repo>/fpga/ ../
$ make
$ make install
$ make x310_rfnoc_image_core

However, I encountered an error right at the beginning of the process, which seems to be related to the clocks. I've tried modifying gain.yml and x310_rfnoc_image_core.yml files, but nothing has worked.

I am using UHD 4.6, and I couldn't find any updated documentation for this version. Here's a summary of the errors I face:

1. If I run the command without changing file parameters:

   ERROR: [Synth 8-448] named port connection 'gtrefclk' does not exist for instance 'core_support_i' of module 'one_gig_eth_pcs_pma_support'
   ERROR: [Synth 8-448] named port connection 'gtrefclk_bufg' does not exist for instance 'core_support_i' of module 'one_gig_eth_pcs_pma_support'
   ERROR: [Synth 8-6156] failed synthesizing module 'one_gige_phy'
   ERROR: [Synth 8-6156] failed synthesizing module 'x300_sfpp_io_core'
   ERROR: [Synth 8-6156] failed synthesizing module 'x300'
   ERROR: [Common 17-69] ...
   
   

2. If I change clk_domains and add:

   codesrcblk: _device_, srcport: ce, dstblk: gain0, dstport: ce
   
   

   I get:

   [ERR] 1 Unresolved clk domain(s)
   [ERR] (_device_-> gain0-ce)
   [ERR] Source or destination domain not found
   
   

3. If I change the clk_domains from ce to rfnoc_chdr:

   ERROR: [synth 8-1031] gain0_rfnoc_chdr_clk is not declared [../../x310_rfnoc_image_core.v:1216]
   ERROR: [Common 17-69] Command failed ...
   
   

I’ve also tried other configurations, but none seem to work. Interestingly, I can build images for RFNoC blocks (FFT, FIR, etc.), but not for out-of-tree (OOT) blocks.

Any guidance or advice would be greatly appreciated.

Thank you!

Hi Martin,

Thanks a lot for your help! I followed your instructions, and it really solved my previous issue.

I'm currently working with the master branch, and after running the command:

make x310_rfnoc_image_core

I successfully generated the file:

x310_rfnoc_image_core.bit

I uploaded the .bit file to the SDR, but now I’m unable to interface with it.

I tried using uhd_usrp_probe, but it doesn’t detect the SDR. I also tried specifying the device address as an argument, but it still didn’t work.

Could you please advise on how to resolve this?

Hi, I successfully managed to implement the example block.
Now, I would like to create my own example block. I'm working on the master version, as per your recommendation.
Is there any documentation available for this process?

I tried to use the following command:

python3 <repo>/host/utils/rfnoc_blocktool/rfnoc_create_verilog.py -c ~/rfnoc-demo/blocks/demo.yml -d ~/rfnoc-demo/fpga/rfnoc_block_demo  

However, I noticed that this file does not exist in this version. Is there an alternative way to achieve this?

I would greatly appreciate any documentation or explanation on how to build a new block for RFNoC.

Hi Martin,

Thank you very much,

I would be happy if you could explain to me how I can make the folder  "fpga/ip" like the rfnoc-gain

Elkana