Dear all, I plan to use an B210 USRP as a downconverter (signal comes in from one antenna at f0, same signal goes out to another antenna at f1), while we also transmit a second signal at f2. Since we are using an embedded ARMv7 platform (Jetson K1 from NVIDIA) we are most concerned with efficient use of (poor) CPU capabilities. If we do everything on the host, the downconversion alone eats 3 out of 4 CPU cores we have, leaving very little for the other job at f2 :( Therefore we would like to shift downconversion to the FPGA. Is there anybody out there who has already done this and is willing to share the patched firmware? Does anybody have an estimate on the effort required? It looks like a trivial change (push samples from here to there) but since I am not an FPGA programmer I might easily overlook troubles ahead. Thanks, Claudio -- Claudio Cicconetti, PhD Software Engineer - MBI S.r.l. - Pisa, Italy http://about.me/ccicconetti

I am not very familiar with the requirements for a DDC (Digital down converter) but if you can do it on a FPGA would'n you be able to do it on the GPU of the Jetson K1 using CUDA? There data transfer rates might be the issue to the GPU and back but it will free up the CPU mostly. If you are neither familiar with FPGA programming or GPU programming, then at least the learning curve is about even. Regards, On Thu, Jan 29, 2015 at 10:52 AM, Claudio Cicconetti via USRP-users < usrp-users@lists.ettus.com> wrote: > Dear all, > I plan to use an B210 USRP as a downconverter (signal comes in from one > antenna at f0, same signal goes out to another antenna at f1), while we > also transmit a second signal at f2. > > Since we are using an embedded ARMv7 platform (Jetson K1 from NVIDIA) we > are most concerned with efficient use of (poor) CPU capabilities. > > If we do everything on the host, the downconversion alone eats 3 out of > 4 CPU cores we have, leaving very little for the other job at f2 :( > Therefore we would like to shift downconversion to the FPGA. > > Is there anybody out there who has already done this and is willing to > share the patched firmware? > > Does anybody have an estimate on the effort required? It looks like a > trivial change (push samples from here to there) but since I am not an > FPGA programmer I might easily overlook troubles ahead. > > Thanks, > Claudio > > -- > Claudio Cicconetti, PhD > Software Engineer - MBI S.r.l. - Pisa, Italy > http://about.me/ccicconetti > > > _______________________________________________ > USRP-users mailing list > USRP-users@lists.ettus.com > http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com >

Dear Carel, Thank you for the fast and relevant comment! Unfortunately, there are a couple of issues with your proposed solution. Firstly, since I need a sustained sampling rate for the DDC (at least 10 Msamples/s) I believe copying back and forth the samples between CPU host memory and CUDA memory would nullify any advantage brought by this approach. (btw things would be different if we could use GPU Direct, which can be used with some specialized network cards to take packets directly into the GPU -> this is not the case with USB3 on a Jetson K1) Secondly, I need the GPU fully for the other waveform which I need to operate at f2 concurrently with DDC. Best regards, Claudio On 01/29/2015 10:16 AM, Carel Combrink wrote: > I am not very familiar with the requirements for a DDC (Digital down > converter) but if you can do it on a FPGA would'n you be able to do it on > the GPU of the Jetson K1 using CUDA? > > There data transfer rates might be the issue to the GPU and back but it > will free up the CPU mostly. > > If you are neither familiar with FPGA programming or GPU programming, then > at least the learning curve is about even. > > Regards, > > On Thu, Jan 29, 2015 at 10:52 AM, Claudio Cicconetti via USRP-users < > usrp-users@lists.ettus.com> wrote: > >> Dear all, >> I plan to use an B210 USRP as a downconverter (signal comes in from one >> antenna at f0, same signal goes out to another antenna at f1), while we >> also transmit a second signal at f2. >> >> Since we are using an embedded ARMv7 platform (Jetson K1 from NVIDIA) we >> are most concerned with efficient use of (poor) CPU capabilities. >> >> If we do everything on the host, the downconversion alone eats 3 out of >> 4 CPU cores we have, leaving very little for the other job at f2 :( >> Therefore we would like to shift downconversion to the FPGA. >> >> Is there anybody out there who has already done this and is willing to >> share the patched firmware? >> >> Does anybody have an estimate on the effort required? It looks like a >> trivial change (push samples from here to there) but since I am not an >> FPGA programmer I might easily overlook troubles ahead. >> >> Thanks, >> Claudio >> >> -- >> Claudio Cicconetti, PhD >> Software Engineer - MBI S.r.l. - Pisa, Italy >> http://about.me/ccicconetti >> >> >> _______________________________________________ >> USRP-users mailing list >> USRP-users@lists.ettus.com >> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com >> >

Claudio, You're going to have to explain more about the application to get any useful data back. For example what frequencies are f0/1/2? Bandwidths and modulation types? Do you need to combine the "f1" signal with the "f2" signal to use the same Tx antenna? What functionality exactly are you including in "downconversion"?..because what most people think of as down conversion can be done pretty much entirely on the USRP already. -Ian On Jan 29, 2015, at 12:52 AM, Claudio Cicconetti via USRP-users <usrp-users@lists.ettus.com> wrote: > Dear all, > I plan to use an B210 USRP as a downconverter (signal comes in from one > antenna at f0, same signal goes out to another antenna at f1), while we > also transmit a second signal at f2. > > Since we are using an embedded ARMv7 platform (Jetson K1 from NVIDIA) we > are most concerned with efficient use of (poor) CPU capabilities. > > If we do everything on the host, the downconversion alone eats 3 out of > 4 CPU cores we have, leaving very little for the other job at f2 :( > Therefore we would like to shift downconversion to the FPGA. > > Is there anybody out there who has already done this and is willing to > share the patched firmware? > > Does anybody have an estimate on the effort required? It looks like a > trivial change (push samples from here to there) but since I am not an > FPGA programmer I might easily overlook troubles ahead. > > Thanks, > Claudio > > -- > Claudio Cicconetti, PhD > Software Engineer - MBI S.r.l. - Pisa, Italy > http://about.me/ccicconetti > > > _______________________________________________ > USRP-users mailing list > USRP-users@lists.ettus.com > http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com

Dear Ian, Thank you for your questions, I apologize for providing incomplete data. The Jetson+B210 will be used for two SDR applications: Application#1 (DDC): signal arrives at f0 = 2193 MHz, must go out at f1 = any in [950 MHz, 2150 MHz]. No processing is required on the signal except for the frequency shift (which can be as little as 43 MHz) Application#2: DSP done on GPU, must transmit at f2 = 2 GHz The two applications are expected to run at the same time but are otherwise are totally independent. As you suggest, most of the job for Application#1 is done already by USRP. In fact, the host code is just a few C++/Python lines. The only problem is: copying samples to/from UHD consumes non-negligible resources as compared to the scarce computation power of the Jetson K1. Best regards, Claudio On 01/30/2015 08:40 AM, Ian Buckley wrote: > Claudio, > You're going to have to explain more about the application to get any useful data back. > For example what frequencies are f0/1/2? Bandwidths and modulation types? > Do you need to combine the "f1" signal with the "f2" signal to use the same Tx antenna? > What functionality exactly are you including in "downconversion"?..because what most people think of as down conversion can be done pretty much entirely on the USRP already. > > -Ian > > > On Jan 29, 2015, at 12:52 AM, Claudio Cicconetti via USRP-users <usrp-users@lists.ettus.com> wrote: > >> Dear all, >> I plan to use an B210 USRP as a downconverter (signal comes in from one >> antenna at f0, same signal goes out to another antenna at f1), while we >> also transmit a second signal at f2. >> >> Since we are using an embedded ARMv7 platform (Jetson K1 from NVIDIA) we >> are most concerned with efficient use of (poor) CPU capabilities. >> >> If we do everything on the host, the downconversion alone eats 3 out of >> 4 CPU cores we have, leaving very little for the other job at f2 :( >> Therefore we would like to shift downconversion to the FPGA. >> >> Is there anybody out there who has already done this and is willing to >> share the patched firmware? >> >> Does anybody have an estimate on the effort required? It looks like a >> trivial change (push samples from here to there) but since I am not an >> FPGA programmer I might easily overlook troubles ahead. >> >> Thanks, >> Claudio >> >> -- >> Claudio Cicconetti, PhD >> Software Engineer - MBI S.r.l. - Pisa, Italy >> http://about.me/ccicconetti >> >> >> _______________________________________________ >> USRP-users mailing list >> USRP-users@lists.ettus.com >> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com >

Please note that both TX paths oft he B210 share one LO. So it will not work to transmit at 2 GHz and 950 MHz at the same time. Both signals must fit with their full bandwidth into the bandwidth that is given by the sampling rate, what usually is nor more than 56 MHz. The mentioned frequencies make me think that your signals may have to do with television signals. Those usually occupy some MHz, up to 20 MHz. So not very much space to handle two of them in a 56 MHz bandwidth. The same applies for the two receivers, they can act independently from the transmitter, but the restriction for two RX signals applies like for two TX signals, they share one LO. The intention of the transceiver chips was MIMO in wireless data, like CDMA, LTE, WIMAX. Hence the common LOs. Ralph. > -----Original Message----- > From: USRP-users [mailto:usrp-users-bounces@lists.ettus.com] On Behalf Of > Claudio Cicconetti via USRP-users > Sent: Friday, January 30, 2015 8:55 AM > To: ianb@ionconcepts.com > Cc: usrp-users@lists.ettus.com > Subject: Re: [USRP-users] B210 as a digital downconverter (in FPGA) > > Dear Ian, > Thank you for your questions, I apologize for providing incomplete data. > > The Jetson+B210 will be used for two SDR applications: > > Application#1 (DDC): signal arrives at f0 = 2193 MHz, must go out at f1 = any in > [950 MHz, 2150 MHz]. No processing is required on the signal except for the > frequency shift (which can be as little as 43 MHz) > > Application#2: DSP done on GPU, must transmit at f2 = 2 GHz > > The two applications are expected to run at the same time but are otherwise > are totally independent. > > As you suggest, most of the job for Application#1 is done already by USRP. In > fact, the host code is just a few C++/Python lines. The only problem is: > copying samples to/from UHD consumes non-negligible resources as > compared to the scarce computation power of the Jetson K1. > > Best regards, > Claudio > > > On 01/30/2015 08:40 AM, Ian Buckley wrote: > > Claudio, > > You're going to have to explain more about the application to get any > useful data back. > > For example what frequencies are f0/1/2? Bandwidths and modulation > types? > > Do you need to combine the "f1" signal with the "f2" signal to use the same > Tx antenna? > > What functionality exactly are you including in > "downconversion"?..because what most people think of as down conversion > can be done pretty much entirely on the USRP already. > > > > -Ian > > > > > > On Jan 29, 2015, at 12:52 AM, Claudio Cicconetti via USRP-users <usrp- > users@lists.ettus.com> wrote: > > > >> Dear all, > >> I plan to use an B210 USRP as a downconverter (signal comes in from > >> one antenna at f0, same signal goes out to another antenna at f1), > >> while we also transmit a second signal at f2. > >> > >> Since we are using an embedded ARMv7 platform (Jetson K1 from > NVIDIA) > >> we are most concerned with efficient use of (poor) CPU capabilities. > >> > >> If we do everything on the host, the downconversion alone eats 3 out > >> of > >> 4 CPU cores we have, leaving very little for the other job at f2 :( > >> Therefore we would like to shift downconversion to the FPGA. > >> > >> Is there anybody out there who has already done this and is willing > >> to share the patched firmware? > >> > >> Does anybody have an estimate on the effort required? It looks like a > >> trivial change (push samples from here to there) but since I am not > >> an FPGA programmer I might easily overlook troubles ahead. > >> > >> Thanks, > >> Claudio > >> > >> -- > >> Claudio Cicconetti, PhD > >> Software Engineer - MBI S.r.l. - Pisa, Italy > >> http://about.me/ccicconetti > >> > >> > >> _______________________________________________ > >> USRP-users mailing list > >> USRP-users@lists.ettus.com > >> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com > > > > > _______________________________________________ > USRP-users mailing list > USRP-users@lists.ettus.com > http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com