Hi all, I am trying to implement a custom demod block in the ddc chain. Everything synthesizes and when I synthesize the demod block by itself I am able to meet the 10 ns timing constraint. However when I use my custom ddc module with the USRP source code, the synthesizer is not able to meet the timing requirements and the critical path of delay shows up as one of the USRP source modules which I haven't touched (namely the sfc module). Is there any reason for this and how do I solve this? Thanks, Hrishikesh Shelar

You don't say which USRP model you are working with, but most have critical timing paths that are easily disturbed when you add further logic. Some of the USRP's with smaller FPGA's are quite heavily utilized and timing performance can decrease quite rapidly as the remaining logic resources are consumed. Some things to look into immediately: Has your block got registers close or at the edge of it's interface with the surrounding logic? This is good practice to prevent combinatorial paths from your blocks combining with existing paths in the USRP and becoming longer. Take a look at the surrounding interfacing logic and estimate what logic depth it has before you reach a register to see if it's appropriate to add further registers. Does your block directly interface with FPGA pins? Because these pins are physically fixed in position, this can cause long nets to traverse the FPGA to get to your logic and/or the logic it interfaces with. Additional registers to pipeline such paths are advised. The standard USRP image has/can have extra features you might not need; A TX DUC chain or a second RX DDC chain. If you won't need these in your project then prune them from the code to free up the logic resources they consume. The less logic used in the FPGA, the easier it is to close timing, QOR rolls off rapidly as the FPGA nears being full. What ever failing paths are reported in the .twr file in the build directory, take a look at them in detail. Look for any net that contributes a large portion of the delay. This maybe a sign of high fanout or a long trace that may need pipelining etc. Also check the path has not got a large number of logic levels that make timing closure unlikely. -ian On Aug 19, 2013, at 3:34 PM, Hrishikesh Shelar <hshelar@umich.edu> wrote: > Hi all, > > I am trying to implement a custom demod block in the ddc chain. Everything synthesizes and when I synthesize the demod block by itself I am able to meet the 10 ns timing constraint. However when I use my custom ddc module with the USRP source code, the synthesizer is not able to meet the timing requirements and the critical path of delay shows up as one of the USRP source modules which I haven't touched (namely the sfc module). Is there any reason for this and how do I solve this? > > Thanks, > Hrishikesh Shelar > _______________________________________________ > USRP-users mailing list > USRP-users@lists.ettus.com > http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com