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Discussion and technical support related to USRP, UHD, RFNoC
View all threadsRx performance degraded in TDD using X310+SBX, ATR setting or what else?
Dear USRP users and experts,
Using X310+SBX, I'm building a TDD system with predefined pattern of Tx and
Rx time slots:
Tx: using tx_metadata_t to specify the transmitting time and end of
transmitting
Rx: always streaming, discarding the i/q samples in the Tx slots
Observations:
- When the Tx is completely off, the Rx demodulation performance is very
good. The noise figure of 3~5dB can achieved with maximum 37.5dB Rx gain,
which is indicated by the estimated SNR in my demodulation algorithm as
well as the simple PSD observation. - When the Tx is on according to the TDD pattern. The receiver sensitivity
becomes tens of dB poorer, although in the Rx slots I'm sure there is no Tx
signal scheduled.
I tried the ATR settings in my earlier post:
http://lists.ettus.com/pipermail/usrp-users_lists.ettus.com/2015-August/015436.html
BUT it seems doesn't help.
I'd eager to know how to make the optimal configuration for
interference-free TDD operation. Thanks.
Bests, Hanwen
On 03/31/2016 05:27 PM, hanwen via USRP-users wrote:
Dear USRP users and experts,
Using X310+SBX, I'm building a TDD system with predefined pattern of
Tx and Rx time slots:
Tx: using tx_metadata_t to specify the transmitting time and end of
transmitting
Rx: always streaming, discarding the i/q samples in the Tx slots
Observations:
- When the Tx is completely off, the Rx demodulation performance is
very good. The noise figure of 3~5dB can achieved with maximum 37.5dB
Rx gain, which is indicated by the estimated SNR in my demodulation
algorithm as well as the simple PSD observation. - When the Tx is on according to the TDD pattern. The receiver
sensitivity becomes tens of dB poorer, although in the Rx slots I'm
sure there is no Tx signal scheduled.
I tried the ATR settings in my earlier post:
http://lists.ettus.com/pipermail/usrp-users_lists.ettus.com/2015-August/015436.html
BUT it seems doesn't help.
I'd eager to know how to make the optimal configuration for
interference-free TDD operation. Thanks.
Bests, Hanwen
USRP-users mailing list
USRP-users@lists.ettus.com
http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
Try using offset-tuning on TX, to move the TX LO leakage out of your
passband. It may still desense during TX schedule, but that doesn't
matter. I think you're complaining that even when your TDD schedule
isn't using the TX, but with the TX chain turned on, you're getting
de-sense on the RX side? You could also decrease the TX gain
whenever your TDD schedule needs to TX, but that may take too much time
depending on the size of your timeslots.
Hi Hanwen,
to be sure to understand you correctly: You observe that your RX gets
desensitized when you TX at the same time, and only during actual
transmission?
That is expected; semiconductor receivers suffer from compression; for
compression measurement data for the SBX, please refer to the
performance measurements on [1]. Compression is when the nonlinear
elements of the receiver characteristics become significant; if the
power on your input amplifier stays below
Input IP3[dB] - Gain[dB]
you shouldn't see significant compression; the higher you go above that,
the less sensitive your receiver gets.
Best regards,
Marcus
[1] files.ettus.com/performance_data/sbx/
On 31.03.2016 23:27, hanwen via USRP-users wrote:
Dear USRP users and experts,
Using X310+SBX, I'm building a TDD system with predefined pattern of
Tx and Rx time slots:
Tx: using tx_metadata_t to specify the transmitting time and end of
transmitting
Rx: always streaming, discarding the i/q samples in the Tx slots
Observations:
- When the Tx is completely off, the Rx demodulation performance is
very good. The noise figure of 3~5dB can achieved with maximum 37.5dB
Rx gain, which is indicated by the estimated SNR in my demodulation
algorithm as well as the simple PSD observation. - When the Tx is on according to the TDD pattern. The receiver
sensitivity becomes tens of dB poorer, although in the Rx slots I'm
sure there is no Tx signal scheduled.
I tried the ATR settings in my earlier
post: http://lists.ettus.com/pipermail/usrp-users_lists.ettus.com/2015-August/015436.html
BUT it seems doesn't help.
I'd eager to know how to make the optimal configuration for
interference-free TDD operation. Thanks.
Bests, Hanwen
USRP-users mailing list
USRP-users@lists.ettus.com
http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
Thanks to you two Marcus :)
The design is in TDD and TDMA mode, the Tx and Rx are scheduled in
non-overlapping time slots. If everything works fine, the received signal
should not be affected by the transmission happens earlier at all.
The time slot is 0.5ms including a guard time if 0.15ms. I'm using the new
3.010 UHD and FPGA.
AN UPDATE OF MY OBSERVATION. The problem is that there is strong DC signal
leakaged into the Rx time slot which cause my rx synchronization algrihm
being failed. According to my tx time stamp, the Tx burst should be
finished 0.15ms before the Rx time slot starts, but it clearly generates
residual DC interference into the Rx slot.
I tried to increase the guard time, from a few millisecond high up to 1
second and I saw the leakaged DC is geting weaker until not visible.
So what do you think would be the cause of such lekaged DC and how could it
be removed to let me have a clean Rx time slot.
Br, Hanwen
2016-03-31 23:57 GMT+02:00 Marcus Müller usrp-users@lists.ettus.com:
Hi Hanwen,
to be sure to understand you correctly: You observe that your RX gets
desensitized when you TX at the same time, and only during actual
transmission?
That is expected; semiconductor receivers suffer from compression; for
compression measurement data for the SBX, please refer to the performance
measurements on [1]. Compression is when the nonlinear elements of the
receiver characteristics become significant; if the power on your input
amplifier stays below
Input IP3[dB] - Gain[dB]
you shouldn't see significant compression; the higher you go above that,
the less sensitive your receiver gets.
Best regards,
Marcus
[1] files.ettus.com/performance_data/sbx/
On 31.03.2016 23:27, hanwen via USRP-users wrote:
Dear USRP users and experts,
Using X310+SBX, I'm building a TDD system with predefined pattern of Tx
and Rx time slots:
Tx: using tx_metadata_t to specify the transmitting time and end of
transmitting
Rx: always streaming, discarding the i/q samples in the Tx slots
Observations:
- When the Tx is completely off, the Rx demodulation performance is very
good. The noise figure of 3~5dB can achieved with maximum 37.5dB Rx gain,
which is indicated by the estimated SNR in my demodulation algorithm as
well as the simple PSD observation. - When the Tx is on according to the TDD pattern. The receiver
sensitivity becomes tens of dB poorer, although in the Rx slots I'm sure
there is no Tx signal scheduled.
I tried the ATR settings in my earlier post:
http://lists.ettus.com/pipermail/usrp-users_lists.ettus.com/2015-August/015436.html
http://lists.ettus.com/pipermail/usrp-users_lists.ettus.com/2015-August/015436.html
BUT it seems doesn't help.
I'd eager to know how to make the optimal configuration for
interference-free TDD operation. Thanks.
Bests, Hanwen
USRP-users mailing listUSRP-users@lists.ettus.comhttp://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
USRP-users mailing list
USRP-users@lists.ettus.com
http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
Hi Hanwen,
your DC is probably LO leakage. An elegant way of dealing with that is
offset tuning:
offset tuning
So, your LO leakage happens at the LO frequency, f_RF. You could use a
non-zero f_offset to move the TX LO out of the observed band, given your
sampling rates aren't close to the master clock rate.
What is your sampling rate, and your signal bandwidths?
Best regards,
Marcus
On 01.04.2016 21:43, hanwen wrote:
Thanks to you two Marcus :)
The design is in TDD and TDMA mode, the Tx and Rx are scheduled in
non-overlapping time slots. If everything works fine, the received
signal should not be affected by the transmission happens earlier at all.
The time slot is 0.5ms including a guard time if 0.15ms. I'm using
the new 3.010 UHD and FPGA.
AN UPDATE OF MY OBSERVATION. The problem is that there is strong DC
signal leakaged into the Rx time slot which cause my rx
synchronization algrihm being failed. According to my tx time stamp,
the Tx burst should be finished 0.15ms before the Rx time slot starts,
but it clearly generates residual DC interference into the Rx slot.
I tried to increase the guard time, from a few millisecond high up to
1 second and I saw the leakaged DC is geting weaker until not visible.
So what do you think would be the cause of such lekaged DC and how
could it be removed to let me have a clean Rx time slot.
Br, Hanwen
2016-03-31 23:57 GMT+02:00 Marcus Müller <usrp-users@lists.ettus.com
mailto:usrp-users@lists.ettus.com>:
Hi Hanwen,
to be sure to understand you correctly: You observe that your RX
gets desensitized when you TX at the same time, and only during
actual transmission?
That is expected; semiconductor receivers suffer from compression;
for compression measurement data for the SBX, please refer to the
performance measurements on [1]. Compression is when the nonlinear
elements of the receiver characteristics become significant; if
the power on your input amplifier stays below
Input IP3[dB] - Gain[dB]
you shouldn't see significant compression; the higher you go above
that, the less sensitive your receiver gets.
Best regards,
Marcus
[1] files.ettus.com/performance_data/sbx/
<http://files.ettus.com/performance_data/sbx/>
On 31.03.2016 23:27, hanwen via USRP-users wrote:
Dear USRP users and experts,
Using X310+SBX, I'm building a TDD system with predefined pattern
of Tx and Rx time slots:
Tx: using tx_metadata_t to specify the transmitting time and end
of transmitting
Rx: always streaming, discarding the i/q samples in the Tx slots
Observations:
1. When the Tx is completely off, the Rx demodulation performance
is very good. The noise figure of 3~5dB can achieved with maximum
37.5dB Rx gain, which is indicated by the estimated SNR in my
demodulation algorithm as well as the simple PSD observation.
2. When the Tx is on according to the TDD pattern. The receiver
sensitivity becomes tens of dB poorer, although in the Rx slots
I'm sure there is no Tx signal scheduled.
I tried the ATR settings in my earlier
post: http://lists.ettus.com/pipermail/usrp-users_lists.ettus.com/2015-August/015436.html
BUT it seems doesn't help.
I'd eager to know how to make the optimal configuration for
interference-free TDD operation. Thanks.
Bests, Hanwen
_______________________________________________
USRP-users mailing list
USRP-users@lists.ettus.com <mailto:USRP-users@lists.ettus.com>
http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
_______________________________________________
USRP-users mailing list
USRP-users@lists.ettus.com <mailto:USRP-users@lists.ettus.com>
http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
Hi Marcus, thanks for the quick response.
My sampling rate is 12.5MS/s, and the signal is ranging from 3~9MHz
configurable.The carrier frequnecy is 2.6GHz.
I forgot to mention that I tried the offset tuning and yes, by doing it at
Tx, the strong DC can be shifted to a non-DC frequency, say in the guard
band outside of my useful signal. I could then remove it simply by a FIR
LPF at Rx.
BUT, the DC leakage is still there and sampled by ADC which is wasting the
Rx dynamic range. I want it to be completely removed.
Basically, I'm still curious that why the DC leakage is still there in the
Rx time slot, although the Tx transmission is finished earlier in the Tx
slot. I do observed that the DC leakage was fading away along with time but
it is too slow (needs many milliseconds). The DC should disappear right
after the Tx end_of_burst. I'd like to know how it could be done.
Br, Hanwen
2016-04-01 22:18 GMT+02:00 Marcus Müller marcus.mueller@ettus.com:
Hi Hanwen,
your DC is probably LO leakage. An elegant way of dealing with that is
offset tuning:
[image: offset tuning]
So, your LO leakage happens at the LO frequency, f_RF. You could use a
non-zero f_offset to move the TX LO out of the observed band, given your
sampling rates aren't close to the master clock rate.
What is your sampling rate, and your signal bandwidths?
Best regards,
Marcus
On 01.04.2016 21:43, hanwen wrote:
Thanks to you two Marcus :)
The design is in TDD and TDMA mode, the Tx and Rx are scheduled in
non-overlapping time slots. If everything works fine, the received signal
should not be affected by the transmission happens earlier at all.
The time slot is 0.5ms including a guard time if 0.15ms. I'm using the
new 3.010 UHD and FPGA.
AN UPDATE OF MY OBSERVATION. The problem is that there is strong DC signal
leakaged into the Rx time slot which cause my rx synchronization algrihm
being failed. According to my tx time stamp, the Tx burst should be
finished 0.15ms before the Rx time slot starts, but it clearly generates
residual DC interference into the Rx slot.
I tried to increase the guard time, from a few millisecond high up to 1
second and I saw the leakaged DC is geting weaker until not visible.
So what do you think would be the cause of such lekaged DC and how could
it be removed to let me have a clean Rx time slot.
Br, Hanwen
2016-03-31 23:57 GMT+02:00 Marcus Müller usrp-users@lists.ettus.com:
Hi Hanwen,
to be sure to understand you correctly: You observe that your RX gets
desensitized when you TX at the same time, and only during actual
transmission?
That is expected; semiconductor receivers suffer from compression; for
compression measurement data for the SBX, please refer to the performance
measurements on [1]. Compression is when the nonlinear elements of the
receiver characteristics become significant; if the power on your input
amplifier stays below
Input IP3[dB] - Gain[dB]
you shouldn't see significant compression; the higher you go above that,
the less sensitive your receiver gets.
Best regards,
Marcus
[1] files.ettus.com/performance_data/sbx/
On 31.03.2016 23:27, hanwen via USRP-users wrote:
Dear USRP users and experts,
Using X310+SBX, I'm building a TDD system with predefined pattern of Tx
and Rx time slots:
Tx: using tx_metadata_t to specify the transmitting time and end of
transmitting
Rx: always streaming, discarding the i/q samples in the Tx slots
Observations:
- When the Tx is completely off, the Rx demodulation performance is very
good. The noise figure of 3~5dB can achieved with maximum 37.5dB Rx gain,
which is indicated by the estimated SNR in my demodulation algorithm as
well as the simple PSD observation. - When the Tx is on according to the TDD pattern. The receiver
sensitivity becomes tens of dB poorer, although in the Rx slots I'm sure
there is no Tx signal scheduled.
I tried the ATR settings in my earlier post:
http://lists.ettus.com/pipermail/usrp-users_lists.ettus.com/2015-August/015436.html
http://lists.ettus.com/pipermail/usrp-users_lists.ettus.com/2015-August/015436.html
BUT it seems doesn't help.
I'd eager to know how to make the optimal configuration for
interference-free TDD operation. Thanks.
Bests, Hanwen
USRP-users mailing listUSRP-users@lists.ettus.comhttp://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
USRP-users mailing list
USRP-users@lists.ettus.com
http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
On 04/01/2016 10:27 PM, hanwen via USRP-users wrote:
Hi Marcus, thanks for the quick response.
My sampling rate is 12.5MS/s, and the signal is ranging from 3~9MHz
configurable.The carrier frequnecy is 2.6GHz.
I forgot to mention that I tried the offset tuning and yes, by doing
it at Tx, the strong DC can be shifted to a non-DC frequency, say in
the guard band outside of my useful signal. I could then remove it
simply by a FIR LPF at Rx.
BUT, the DC leakage is still there and sampled by ADC which is wasting
the Rx dynamic range. I want it to be completely removed.
Basically, I'm still curious that why the DC leakage is still there in
the Rx time slot, although the Tx transmission is finished earlier in
the Tx slot. I do observed that the DC leakage was fading away along
with time but it is too slow (needs many milliseconds). The DC should
disappear right after the Tx end_of_burst. I'd like to know how it
could be done.
Br, Hanwen
I can see two solutions off the top of my head:
(A) Clamp the RF gain of the TX chain some short time after you've
indicated tx_eob
There's no way to fully shut down the analog bits and then
bring them up again without incurring other types of transients, and would
likely result in horribleness in a TDD system--because that
hardware cannot be turn on/off fast enough. So, the synthesizer is
still running
between bursts, so whatever leakage the mixer is going to have
will be present.
(B) Move the DC offset to a location outside your passband, and use a
bandpass analog filter on the TX output. Analog mixers and RF chains
in general have undesired outputs--that is true in
purpose-built radios as well, but they design the output filters in an
application-specific
way. For a not-for-a-specific-application radio like an SDR,
all that type of plumbing needs to be provided as part of the application.
2016-04-01 22:18 GMT+02:00 Marcus Müller <marcus.mueller@ettus.com
mailto:marcus.mueller@ettus.com>:
Hi Hanwen,
your DC is probably LO leakage. An elegant way of dealing with
that is offset tuning:
offset tuning
So, your LO leakage happens at the LO frequency, f_RF. You could
use a non-zero f_offset to move the TX LO out of the observed
band, given your sampling rates aren't close to the master clock rate.
What is your sampling rate, and your signal bandwidths?
Best regards,
Marcus
On 01.04.2016 21:43, hanwen wrote:
Thanks to you two Marcus :)
The design is in TDD and TDMA mode, the Tx and Rx are scheduled
in non-overlapping time slots. If everything works fine, the
received signal should not be affected by the transmission
happens earlier at all.
The time slot is 0.5ms including a guard time if 0.15ms. I'm
using the new 3.010 UHD and FPGA.
AN UPDATE OF MY OBSERVATION. The problem is that there is strong
DC signal leakaged into the Rx time slot which cause my rx
synchronization algrihm being failed. According to my tx time
stamp, the Tx burst should be finished 0.15ms before the Rx time
slot starts, but it clearly generates residual DC interference
into the Rx slot.
I tried to increase the guard time, from a few millisecond high
up to 1 second and I saw the leakaged DC is geting weaker until
not visible.
So what do you think would be the cause of such lekaged DC and
how could it be removed to let me have a clean Rx time slot.
Br, Hanwen
2016-03-31 23:57 GMT+02:00 Marcus Müller
<usrp-users@lists.ettus.com <mailto:usrp-users@lists.ettus.com>>:
Hi Hanwen,
to be sure to understand you correctly: You observe that your
RX gets desensitized when you TX at the same time, and only
during actual transmission?
That is expected; semiconductor receivers suffer from
compression; for compression measurement data for the SBX,
please refer to the performance measurements on [1].
Compression is when the nonlinear elements of the receiver
characteristics become significant; if the power on your
input amplifier stays below
Input IP3[dB] - Gain[dB]
you shouldn't see significant compression; the higher you go
above that, the less sensitive your receiver gets.
Best regards,
Marcus
[1] files.ettus.com/performance_data/sbx/
<http://files.ettus.com/performance_data/sbx/>
On 31.03.2016 23:27, hanwen via USRP-users wrote:
Dear USRP users and experts,
Using X310+SBX, I'm building a TDD system with predefined
pattern of Tx and Rx time slots:
Tx: using tx_metadata_t to specify the transmitting time and
end of transmitting
Rx: always streaming, discarding the i/q samples in the Tx slots
Observations:
1. When the Tx is completely off, the Rx demodulation
performance is very good. The noise figure of 3~5dB can
achieved with maximum 37.5dB Rx gain, which is indicated by
the estimated SNR in my demodulation algorithm as well as
the simple PSD observation.
2. When the Tx is on according to the TDD pattern. The
receiver sensitivity becomes tens of dB poorer, although in
the Rx slots I'm sure there is no Tx signal scheduled.
I tried the ATR settings in my earlier post:
http://lists.ettus.com/pipermail/usrp-users_lists.ettus.com/2015-August/015436.html
BUT it seems doesn't help.
I'd eager to know how to make the optimal configuration for
interference-free TDD operation. Thanks.
Bests, Hanwen
_______________________________________________
USRP-users mailing list
USRP-users@lists.ettus.com <mailto:USRP-users@lists.ettus.com>
http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
_______________________________________________
USRP-users mailing list
USRP-users@lists.ettus.com <mailto:USRP-users@lists.ettus.com>
http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
USRP-users mailing list
USRP-users@lists.ettus.com
http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
Hi Marcus,
I tried the offset tuning today and found the strongest pike can be shifted
to a non-DC frequency only by the offset tuning at Rx, which means that
this components is actually generated in the receiver.
But however, this Rx DC only appear when I do transmission and the strength
can be reduced by increasing the time between Tx and Rx slots.
In summary, it looks like there is a timely decreasing DC component
generated by Rx which is however invoked by Tx operation before. I'm
curious that such a transient take so long (ten's of milliseconds) which
bring's trouble to fast TDMA switch we need.
I'm using 3.010 firmware and uhd-master.
Br, Hanwen
2016-04-02 4:49 GMT+02:00 Marcus D. Leech via USRP-users <
usrp-users@lists.ettus.com>:
On 04/01/2016 10:27 PM, hanwen via USRP-users wrote:
Hi Marcus, thanks for the quick response.
My sampling rate is 12.5MS/s, and the signal is ranging from 3~9MHz
configurable.The carrier frequnecy is 2.6GHz.
I forgot to mention that I tried the offset tuning and yes, by doing it at
Tx, the strong DC can be shifted to a non-DC frequency, say in the guard
band outside of my useful signal. I could then remove it simply by a FIR
LPF at Rx.
BUT, the DC leakage is still there and sampled by ADC which is wasting the
Rx dynamic range. I want it to be completely removed.
Basically, I'm still curious that why the DC leakage is still there in the
Rx time slot, although the Tx transmission is finished earlier in the Tx
slot. I do observed that the DC leakage was fading away along with time but
it is too slow (needs many milliseconds). The DC should disappear right
after the Tx end_of_burst. I'd like to know how it could be done.
Br, Hanwen
I can see two solutions off the top of my head:
(A) Clamp the RF gain of the TX chain some short time after you've
indicated tx_eob
There's no way to fully shut down the analog bits and then bring
them up again without incurring other types of transients, and would
likely result in horribleness in a TDD system--because that
hardware cannot be turn on/off fast enough. So, the synthesizer is still
running
between bursts, so whatever leakage the mixer is going to have
will be present.
(B) Move the DC offset to a location outside your passband, and use a
bandpass analog filter on the TX output. Analog mixers and RF chains
in general have undesired outputs--that is true in purpose-built
radios as well, but they design the output filters in an
application-specific
way. For a not-for-a-specific-application radio like an SDR, all
that type of plumbing needs to be provided as part of the application.
2016-04-01 22:18 GMT+02:00 Marcus Müller marcus.mueller@ettus.com:
Hi Hanwen,
your DC is probably LO leakage. An elegant way of dealing with that is
offset tuning:
[image: offset tuning]
So, your LO leakage happens at the LO frequency, f_RF. You could use a
non-zero f_offset to move the TX LO out of the observed band, given your
sampling rates aren't close to the master clock rate.
What is your sampling rate, and your signal bandwidths?
Best regards,
Marcus
On 01.04.2016 21:43, hanwen wrote:
Thanks to you two Marcus :)
The design is in TDD and TDMA mode, the Tx and Rx are scheduled in
non-overlapping time slots. If everything works fine, the received signal
should not be affected by the transmission happens earlier at all.
The time slot is 0.5ms including a guard time if 0.15ms. I'm using the
new 3.010 UHD and FPGA.
AN UPDATE OF MY OBSERVATION. The problem is that there is strong DC
signal leakaged into the Rx time slot which cause my rx synchronization
algrihm being failed. According to my tx time stamp, the Tx burst should be
finished 0.15ms before the Rx time slot starts, but it clearly generates
residual DC interference into the Rx slot.
I tried to increase the guard time, from a few millisecond high up to 1
second and I saw the leakaged DC is geting weaker until not visible.
So what do you think would be the cause of such lekaged DC and how could
it be removed to let me have a clean Rx time slot.
Br, Hanwen
2016-03-31 23:57 GMT+02:00 Marcus Müller usrp-users@lists.ettus.com:
Hi Hanwen,
to be sure to understand you correctly: You observe that your RX gets
desensitized when you TX at the same time, and only during actual
transmission?
That is expected; semiconductor receivers suffer from compression; for
compression measurement data for the SBX, please refer to the performance
measurements on [1]. Compression is when the nonlinear elements of the
receiver characteristics become significant; if the power on your input
amplifier stays below
Input IP3[dB] - Gain[dB]
you shouldn't see significant compression; the higher you go above that,
the less sensitive your receiver gets.
Best regards,
Marcus
[1] files.ettus.com/performance_data/sbx/
On 31.03.2016 23:27, hanwen via USRP-users wrote:
Dear USRP users and experts,
Using X310+SBX, I'm building a TDD system with predefined pattern of Tx
and Rx time slots:
Tx: using tx_metadata_t to specify the transmitting time and end of
transmitting
Rx: always streaming, discarding the i/q samples in the Tx slots
Observations:
- When the Tx is completely off, the Rx demodulation performance is
very good. The noise figure of 3~5dB can achieved with maximum 37.5dB Rx
gain, which is indicated by the estimated SNR in my demodulation algorithm
as well as the simple PSD observation. - When the Tx is on according to the TDD pattern. The receiver
sensitivity becomes tens of dB poorer, although in the Rx slots I'm sure
there is no Tx signal scheduled.
I tried the ATR settings in my earlier post:
http://lists.ettus.com/pipermail/usrp-users_lists.ettus.com/2015-August/015436.html
BUT it seems doesn't help.
I'd eager to know how to make the optimal configuration for
interference-free TDD operation. Thanks.
Bests, Hanwen
USRP-users mailing listUSRP-users@lists.ettus.comhttp://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
USRP-users mailing list
USRP-users@lists.ettus.com
http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
USRP-users mailing listUSRP-users@lists.ettus.comhttp://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
USRP-users mailing list
USRP-users@lists.ettus.com
http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
On 04/04/2016 04:54 PM, hanwen wrote:
Hi Marcus,
I tried the offset tuning today and found the strongest pike can be
shifted to a non-DC frequency only by the offset tuning at Rx, which
means that this components is actually generated in the receiver.
But however, this Rx DC only appear when I do transmission and the
strength can be reduced by increasing the time between Tx and Rx slots.
In summary, it looks like there is a timely decreasing DC component
generated by Rx which is however invoked by Tx operation before. I'm
curious that such a transient take so long (ten's of milliseconds)
which bring's trouble to fast TDMA switch we need.
I'm using 3.010 firmware and uhd-master.
Br, Hanwen
There's also DC-offset compensation, which is always running on RX. It
can be disabled--it converges somewhat slowly.
2016-04-02 4:49 GMT+02:00 Marcus D. Leech via USRP-users
<usrp-users@lists.ettus.com mailto:usrp-users@lists.ettus.com>:
On 04/01/2016 10:27 PM, hanwen via USRP-users wrote:
Hi Marcus, thanks for the quick response.
My sampling rate is 12.5MS/s, and the signal is ranging from
3~9MHz configurable.The carrier frequnecy is 2.6GHz.
I forgot to mention that I tried the offset tuning and yes, by
doing it at Tx, the strong DC can be shifted to a non-DC
frequency, say in the guard band outside of my useful signal. I
could then remove it simply by a FIR LPF at Rx.
BUT, the DC leakage is still there and sampled by ADC which is
wasting the Rx dynamic range. I want it to be completely removed.
Basically, I'm still curious that why the DC leakage is still
there in the Rx time slot, although the Tx transmission is
finished earlier in the Tx slot. I do observed that the DC
leakage was fading away along with time but it is too slow (needs
many milliseconds). The DC should disappear right after the Tx
end_of_burst. I'd like to know how it could be done.
Br, Hanwen
I can see two solutions off the top of my head:
(A) Clamp the RF gain of the TX chain some short time after
you've indicated tx_eob
There's no way to fully shut down the analog bits and then
bring them up again without incurring other types of transients,
and would
likely result in horribleness in a TDD system--because
that hardware cannot be turn on/off fast enough. So, the
synthesizer is still running
between bursts, so whatever leakage the mixer is going to
have will be present.
(B) Move the DC offset to a location outside your passband, and
use a bandpass analog filter on the TX output. Analog mixers and
RF chains
in general have undesired outputs--that is true in
purpose-built radios as well, but they design the output filters
in an application-specific
way. For a not-for-a-specific-application radio like an
SDR, all that type of plumbing needs to be provided as part of the
application.
2016-04-01 22:18 GMT+02:00 Marcus Müller
<marcus.mueller@ettus.com <mailto:marcus.mueller@ettus.com>>:
Hi Hanwen,
your DC is probably LO leakage. An elegant way of dealing
with that is offset tuning:
offset tuning
So, your LO leakage happens at the LO frequency, f_RF. You
could use a non-zero f_offset to move the TX LO out of the
observed band, given your sampling rates aren't close to the
master clock rate.
What is your sampling rate, and your signal bandwidths?
Best regards,
Marcus
On 01.04.2016 21:43, hanwen wrote:
Thanks to you two Marcus :)
The design is in TDD and TDMA mode, the Tx and Rx are
scheduled in non-overlapping time slots. If everything works
fine, the received signal should not be affected by the
transmission happens earlier at all.
The time slot is 0.5ms including a guard time if 0.15ms.
I'm using the new 3.010 UHD and FPGA.
AN UPDATE OF MY OBSERVATION. The problem is that there is
strong DC signal leakaged into the Rx time slot which cause
my rx synchronization algrihm being failed. According to my
tx time stamp, the Tx burst should be finished 0.15ms before
the Rx time slot starts, but it clearly generates residual
DC interference into the Rx slot.
I tried to increase the guard time, from a few millisecond
high up to 1 second and I saw the leakaged DC is geting
weaker until not visible.
So what do you think would be the cause of such lekaged DC
and how could it be removed to let me have a clean Rx time slot.
Br, Hanwen
2016-03-31 23:57 GMT+02:00 Marcus Müller
<usrp-users@lists.ettus.com
<mailto:usrp-users@lists.ettus.com>>:
Hi Hanwen,
to be sure to understand you correctly: You observe that
your RX gets desensitized when you TX at the same time,
and only during actual transmission?
That is expected; semiconductor receivers suffer from
compression; for compression measurement data for the
SBX, please refer to the performance measurements on
[1]. Compression is when the nonlinear elements of the
receiver characteristics become significant; if the
power on your input amplifier stays below
Input IP3[dB] - Gain[dB]
you shouldn't see significant compression; the higher
you go above that, the less sensitive your receiver gets.
Best regards,
Marcus
[1] files.ettus.com/performance_data/sbx/
<http://files.ettus.com/performance_data/sbx/>
On 31.03.2016 23:27, hanwen via USRP-users wrote:
Dear USRP users and experts,
Using X310+SBX, I'm building a TDD system with
predefined pattern of Tx and Rx time slots:
Tx: using tx_metadata_t to specify the transmitting
time and end of transmitting
Rx: always streaming, discarding the i/q samples in the
Tx slots
Observations:
1. When the Tx is completely off, the Rx demodulation
performance is very good. The noise figure of 3~5dB can
achieved with maximum 37.5dB Rx gain, which is
indicated by the estimated SNR in my demodulation
algorithm as well as the simple PSD observation.
2. When the Tx is on according to the TDD pattern. The
receiver sensitivity becomes tens of dB poorer,
although in the Rx slots I'm sure there is no Tx signal
scheduled.
I tried the ATR settings in my earlier post:
http://lists.ettus.com/pipermail/usrp-users_lists.ettus.com/2015-August/015436.html
BUT it seems doesn't help.
I'd eager to know how to make the optimal configuration
for interference-free TDD operation. Thanks.
Bests, Hanwen
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