Hi Kit,

My guess is all of the dividers are more than good enough. But...

Since the question of jitter comes up now and then, and since
there are several new dividers in the queue this year, I thought
I'd settle it once and for all and actually measure as many as I
can find.

An added bonus is that Magnus is able and willing to do the same
and that means not only can we compare divider jitter but we can
compare methods to measure divider jitter. In this field validating
and comparing methods is as important as making measurements.

As for pecking order? I don't really know yet. Wait to see if
Peter picks a peck of pulsing picosecond PICs.

/tvb

The performance of the sine to square wave conversion clock shaper
circuit may dominate the divider performance.
Thus an evaluation of the jitter performance of sine to square wave
conversion circuits would also be informative/useful.

If one is using a digital divider in a narrow band PLL the close in
phase noise performance of the divider may be more important than its
phase noise floor, in which case an ECL or CML divider (or at least a
divider using a CML or ECL resynchronising flipflop) may be a better
choice than a TTL or CMOS divider, especially if a low noise diode mixer
is used as a phase detector is used.

Thus characterising divider phase noise may also be useful, although it
may be difficult to do this for divider output frequencies much below
1Mhz or so.

Bruce

Tom Van Baak wrote:

Tom Van Baak wrote:

I think it would be a very good idea.

... and learn from each others methods and misstakes.

We haven't settled the pecking order. To able able to do that we need to
measure and compare.

After that we need to think. It might be that the off the shelf variant
may have some design-issues, but some of them could be surprisingly
simple to overcome by modification (say swapping drivers, disable
signals etc).

So the final pecking order may not be put down after a day in either
Toms or my lab. We would have initial results, but that's all.

Currently I have one assembled TADD-2, one not yeat assembled, and a
HP5328A.

The HP5328A is not the same thing all the time. The input stage depends
on the options it has. Plain HP5328A or having Option 040 or 041 is
making a difference here.

If someone wants me to measure anything else, they would have to send it
to me.

Also, I have some homework to do just to set up logging from any of my
toys. I need to do that. Yes, I am lazy.

Cheers,
Magnus

Bruce Griffiths wrote:

We should standardise some test for estimating the input contribution.
I would prefer using various amplitudes, preferably with a measurement
of achieved slew-rate.

I have reason to beleive that pulse-width factor has great importance in
the produced result for mixer-based measurements. I have not had the
time to make any conclusive measurements or theoretical work for it, it
just looks like that.

Indeed.

It's a pitty that the SIA-3000 stops doing meaningful measurements at 11
MHz... and lower. If someone could tell me how to overcome that, I would
be very greatful.

Cheers,
Magnus

Magnus Danielson wrote:

The input circuit will have an intrinsic jitter plus contributions due
to the input signal slew rate at the threshold crossing.
A resultant measured performance of the form:
trigger jitter~ SQRT( 1E-22 + (1E-4/S)^2) plus other terms
where the actual numbers depend on the particular input clock shaping
circuit may be expected.

Yes, NIST have shown that the mixer input signal should either be a
relatively low distortion sinewave or the duty cycle of a square wave
should be close to 50%.
This may make it difficult to measure the phase noise of those dividers
with outputs that don't have a 50% duty cycle.
Achieving accurate quadrature between the mixer/phase detector inputs
can be critical in classical mixer based systems.

Divider jitter will also have contributions due to aliased noise from
the input signal.

The TSC5120A allows phase noise measurements on signals with frequencies
down to 1MHz.
Classical diode mixer based systems can go somewhat lower in frequency.

For those dividers that have a buffered 10MHz sqare wave output
measurement of the jitter of lower frequency outputs with respect to the
buffered 10MHz output may provide a better measure of divider
performance as the jitter due to the clock conditioning/shaping circuit
should be largely common mode.

Bruce

Bruce,

Bruce Griffiths wrote:

Indeed. This is the basic formula and summation of errors I had in mind.

An indication has been that following a "high jitter" divider by a
divide-by-2 provides a lower jitter than anticipated. Asymmetries in
input clocks have also caused some problems for some dividers again
being improved by the divide-by-2. All according to NIST measurements.
Thus, care should be taken in ensuring this property when measuring.

Indeed. I have been pondering over that aspect myself.

You should realize that I have reasons to believe that the limit is one
of software parameters rather than anything else.

Lacking a TSC5120A or sufficiently similar in my lab...

Indeed, but for most uses it doesn't help as it is the output absolute
jitter which is being seen by the measurement application, so for most
uses it needs to be included in the measurement, where as we of course
is curious in figuring out at which stage the jitter performance is
significantly impaired.

Cheers,
Magnus

I'll use a 5120A for 10M to 5M or 2.5M or 1M cases.

Below that I'm in the same situation as you, with the usual
lab assortment of HP, SRS, Wavecrest, and Pendulum TI
counters. I have logging for all of them; except Wavecrest
but Said has experience with that noisy beast and is already
helping me out (Thanks!).

/tvb

Tom Van Baak wrote:

Mostly 10 MHz and 5 MHz sources would be tested.

I would be interested in whatever you come up with. My logging is at the
unacceptable level. The Pendulum I can log with their software.

A partial GPIB-network spans the backside of the workbench, but it needs
rewiring and more wires.

My preferred platform is however Linux and in particular Debian. Just to
keep things a bit interesting.

Cheers,
Magnus