I wrote a program to interact with my RFNoC block. I stream data to it which it stores into DRAM. I then write a control register and the DRAM is transmitted. I have been testing my block over 100 Gbe using a remote machine and I finally got the results I was expecting. The spectrum looks great. Everything is consistent and works wonderfully. I then rebuilt my application targeted for the RFSoC and use 127.0.0.1 as the target IP. When I do this, the spectrum looks absolutely terrible. Investigating further, I see the DRAM AXI bus gets written with the appropriate data, but the read channel returns absolute garbage. To further complicate things, if I run my program on the external host with 100 Gbe connectivity, and then I run the program locally on the RFSoC, I get the desired output and the DRAM reads are correct. I haven't looked at the DRAM signals directly, but it almost seems like the write enables are disabled when I am running from the RFSoC directly but working fine when ethernet is involved? I am puzzled by this mainly because, as I stated, the only change I have is where the program is running. I would imagine the desired effect should be the same for running on an external machine or on the local one? Any pointers or insight would be appreciated. Thanks, Brian

Hey Brian, sorry for leaving this thread dangling so long. Did you figure something out? This behaviour does indeed sound weird. --M On Sat, May 10, 2025 at 2:36 AM Brian Padalino <bpadalino@gmail.com> wrote: > I wrote a program to interact with my RFNoC block. I stream data to it > which it stores into DRAM. I then write a control register and the DRAM is > transmitted. > > I have been testing my block over 100 Gbe using a remote machine and I > finally got the results I was expecting. The spectrum looks great. > Everything is consistent and works wonderfully. > > I then rebuilt my application targeted for the RFSoC and use 127.0.0.1 as > the target IP. When I do this, the spectrum looks absolutely terrible. > Investigating further, I see the DRAM AXI bus gets written with the > appropriate data, but the read channel returns absolute garbage. > > To further complicate things, if I run my program on the external host > with 100 Gbe connectivity, and then I run the program locally on the RFSoC, > I get the desired output and the DRAM reads are correct. > > I haven't looked at the DRAM signals directly, but it almost seems like > the write enables are disabled when I am running from the RFSoC directly > but working fine when ethernet is involved? > > I am puzzled by this mainly because, as I stated, the only change I have > is where the program is running. I would imagine the desired effect should > be the same for running on an external machine or on the local one? > > Any pointers or insight would be appreciated. > > Thanks, > Brian > _______________________________________________ > USRP-users mailing list -- usrp-users@lists.ettus.com > To unsubscribe send an email to usrp-users-leave@lists.ettus.com >

Hey Martin, On Tue, Jul 1, 2025 at 8:47 AM Martin Braun <martin.braun@ettus.com> wrote: > Hey Brian, > > sorry for leaving this thread dangling so long. Did you figure something > out? This behaviour does indeed sound weird. > Unfortunately I ended up moving on. I noted it as something to look at later, but the main use case is to receive samples over QSFP+ and only set up the RFNoC graph with the arm, so it isn't a showstopper. When I get the base functionality completed, I'll go back and hopefully remember to post back to this thread. Thanks, Brian