Mike
Its well worthwhile estimating the additional jitter due to this effect
when using such a circuit to square up the output of an OCXO:
If the input signal characteristics are:
Frequency 10MHz
Amplitude at the gate input: A = 1.4V pk
Threshold mismatch Vt = 1V
AM noise: Am = -120dBc/Hz
Input signal AM noise bandwidth: BW = 1MHz (eg a low Q bandpass filter).
Rms Output jitter due to AM noise is given by
delta(t) ~ (1/(2PIf))((Vt/A)/(1 + (Vt/A)(Vt/A)))(BW1)^(Am/20))
i.e.
delta(t) ~ 0.5*1.6E-8 *(1E-3) sec
~ 8ps rms.
Wideband AM noise as high as -120dBc/Hz is somewhat higher than is
typical for a good OCXO.
Thus in applications such as a PPS divider this effect is probably
insignificant.
However it may be useful to use a low Q bandpass filter to limit the
integrated AM and PM noise seen at the gate input.
Bruce
Mike Monett wrote:
Message: 3
Date: Fri, 03 Apr 2009 09:04:59 +1300
From: Bruce Griffiths bruce.griffiths@xtra.co.nz
Subject: Re: [time-nuts] Frequency Divider
Hal Murray wrote:
A large resistor connected between the input and output would
accommodate threshold variations better. Even better would be a
feedback loop that adjusts the input bias point to maintain the
output duty cycle at 50%.
Isn't that resistor a feedback loop?
I played with that setup in the lab many years ago. It didn't
work as well as I was expecting. I didn't figure out why it
didn't work better.
Maybe some gain in the feedback path would help. Then we have to
consider stability. Ugh.
Hal
Yes, a resistor connected between the input and output of an
inverter is a feedback loop but the loop gain is relatively low.
With a high amplitude input threshold variations from the nominal
can cause the input protection diodes to conduct.
Once these diodes conduct the output jitter may deteriorate
significantly (it does for HCMOS inverters).
Using a non inverting integrator in the feedback path can
accurately stabilise the duty cycle.
Bruce
The 74HC and 74AC input threshold tolerance is +/- 30%. This means
the threshold can vary from 1.5V to 3.5V with a Vcc of 5V.
This limits the maximum input signal to 3V p-p or +13.5dBm, and
leads to a very subtle flaw discovered in some amazing engineering
work by Martein Bakker, PA3AKE.
If the threshold is not controlled, it can cause AM noise to convert
to PM noise and degrade the jitter. This occurs in the Analog
Devices AD9910 1GHz DDS chip.
Martein Bakker discovered this in his noise analysis, and Kevin
Wheatly gave a nice entry in his blog on how to fix it:
Mike
time-nuts mailing list -- time-nuts@febo.com
To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts
and follow the instructions there.
Correction:
For those who didn't spot it, the formula should have been:
delta(t) ~ (1/(2PIf))((Vt/A)/(1 + (Vt/A)(Vt/A)))*SQRT(BW)*10^(Am/20));
Bruce
Bruce Griffiths wrote:
Mike
Its well worthwhile estimating the additional jitter due to this effect
when using such a circuit to square up the output of an OCXO:
If the input signal characteristics are:
Frequency 10MHz
Amplitude at the gate input: A = 1.4V pk
Threshold mismatch Vt = 1V
AM noise: Am = -120dBc/Hz
Input signal AM noise bandwidth: BW = 1MHz (eg a low Q bandpass filter).
Rms Output jitter due to AM noise is given by
delta(t) ~ (1/(2PIf))((Vt/A)/(1 + (Vt/A)(Vt/A)))(BW1)^(Am/20))
i.e.
delta(t) ~ 0.5*1.6E-8 *(1E-3) sec
~ 8ps rms.
Wideband AM noise as high as -120dBc/Hz is somewhat higher than is
typical for a good OCXO.
Thus in applications such as a PPS divider this effect is probably
insignificant.
However it may be useful to use a low Q bandpass filter to limit the
integrated AM and PM noise seen at the gate input.
Bruce
Mike Monett wrote:
Message: 3
Date: Fri, 03 Apr 2009 09:04:59 +1300
From: Bruce Griffiths bruce.griffiths@xtra.co.nz
Subject: Re: [time-nuts] Frequency Divider
Hal Murray wrote:
A large resistor connected between the input and output would
accommodate threshold variations better. Even better would be a
feedback loop that adjusts the input bias point to maintain the
output duty cycle at 50%.
Isn't that resistor a feedback loop?
I played with that setup in the lab many years ago. It didn't
work as well as I was expecting. I didn't figure out why it
didn't work better.
Maybe some gain in the feedback path would help. Then we have to
consider stability. Ugh.
Hal
Yes, a resistor connected between the input and output of an
inverter is a feedback loop but the loop gain is relatively low.
With a high amplitude input threshold variations from the nominal
can cause the input protection diodes to conduct.
Once these diodes conduct the output jitter may deteriorate
significantly (it does for HCMOS inverters).
Using a non inverting integrator in the feedback path can
accurately stabilise the duty cycle.
Bruce
The 74HC and 74AC input threshold tolerance is +/- 30%. This means
the threshold can vary from 1.5V to 3.5V with a Vcc of 5V.
This limits the maximum input signal to 3V p-p or +13.5dBm, and
leads to a very subtle flaw discovered in some amazing engineering
work by Martein Bakker, PA3AKE.
If the threshold is not controlled, it can cause AM noise to convert
to PM noise and degrade the jitter. This occurs in the Analog
Devices AD9910 1GHz DDS chip.
Martein Bakker discovered this in his noise analysis, and Kevin
Wheatly gave a nice entry in his blog on how to fix it:
Mike
time-nuts mailing list -- time-nuts@febo.com
To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts
and follow the instructions there.
time-nuts mailing list -- time-nuts@febo.com
To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts
and follow the instructions there.