TD
Tijd Dingen
Thu, Jan 6, 2011 7:02 PM
To whom it may concerns,
Currently I am building a DIY frequency counter. Since this is my first serious counter project I am trying to keep things simple, hence It Will Not Be State Of The Art. Maybe a not-too-difficult hobby level counter will be of interest to some, so I'd thought I'd post here...
The architecture in a couple of bulletpoints:
- fpga based as much as possible to keep the parts count down
- coarse counters running at max 200 MHz for now
- interpolation is done using TDC's. The TDC's look suspiciously much like tapped delay lines and are implemented inside the fpga, using mainly the carry chains.
- 10000 continuous time stamps per second
- 500 ps timestamp resolution. And with resolution I mean the smallest resolvable thingy (related to bin size), not precision nor accuracy.
That 500 ps is conservative. I intend to do better than that, but just to give some idea of the starting point... The main thing for now is to get a handle on the DNL of the TDC.
I am currently playing around with some designs in a spartan-6 and a spartan-3e. The spartan-6 design has more promise resolution wise, but it is also not very hobby friendly (bga package). So if this is ever to be built using hobby level soldering skills it will be spartan-3e. The 250k gates devices are available in tqfp-100 package which is doable IMO.
The timestamps are transmitted over usb to the pc for number crunching. The idea is to do some curve fitting to get a frequency estimate, computate Allan Deviation, and do the obligatory plots. With regard to Allan Deviation, as long as I make sure the measurements have zero dead time, I can compute Allan Deviation using the raw time stamps, right?
Also note the glaring lack of a prescaler. This can and will be added at a later date to extend the range of the counter. For now I just want to get the basics working properly first. On the subject of prescalers, does anyone know where to order Hittite parts in low quantities? I noticed on hittite.com you can place an order but if I understand correctly that is only for 10+. Which is probably great if you do a group buy, but not if I want to try out 3 of those, 2 of those, etc...
Another question for those that have already done this ... suppose you have a "good" 10 MHz (OCXO, GPSDO, WhateverO) and want to use that for your reference counter. What is a reasonable low cost method to end up with a 200 MHz clock in a spartan-3e and a 500 MHz clock in a spartan-6? I am currently using the fpga's internal dcm but the added jitter is considerable.
Since I am a newbie when it comes to this time stuff, no doubt there will be plenty of you that have more experience with implementations of counters ... so what are regular pitfalls I should be aware of?
Thank you for your time,
Fred
To whom it may concerns,
Currently I am building a DIY frequency counter. Since this is my first serious counter project I am trying to keep things simple, hence It Will Not Be State Of The Art. Maybe a not-too-difficult hobby level counter will be of interest to some, so I'd thought I'd post here...
The architecture in a couple of bulletpoints:
- fpga based as much as possible to keep the parts count down
- coarse counters running at max 200 MHz for now
- interpolation is done using TDC's. The TDC's look suspiciously much like tapped delay lines and are implemented inside the fpga, using mainly the carry chains.
- 10000 continuous time stamps per second
- 500 ps timestamp resolution. And with resolution I mean the smallest resolvable thingy (related to bin size), not precision nor accuracy.
That 500 ps is conservative. I intend to do better than that, but just to give some idea of the starting point... The main thing for now is to get a handle on the DNL of the TDC.
I am currently playing around with some designs in a spartan-6 and a spartan-3e. The spartan-6 design has more promise resolution wise, but it is also not very hobby friendly (bga package). So if this is ever to be built using hobby level soldering skills it will be spartan-3e. The 250k gates devices are available in tqfp-100 package which is doable IMO.
The timestamps are transmitted over usb to the pc for number crunching. The idea is to do some curve fitting to get a frequency estimate, computate Allan Deviation, and do the obligatory plots. With regard to Allan Deviation, as long as I make sure the measurements have zero dead time, I can compute Allan Deviation using the raw time stamps, right?
Also note the glaring lack of a prescaler. This can and will be added at a later date to extend the range of the counter. For now I just want to get the basics working properly first. On the subject of prescalers, does anyone know where to order Hittite parts in low quantities? I noticed on hittite.com you can place an order but if I understand correctly that is only for 10+. Which is probably great if you do a group buy, but not if I want to try out 3 of those, 2 of those, etc...
Another question for those that have already done this ... suppose you have a "good" 10 MHz (OCXO, GPSDO, WhateverO) and want to use that for your reference counter. What is a reasonable low cost method to end up with a 200 MHz clock in a spartan-3e and a 500 MHz clock in a spartan-6? I am currently using the fpga's internal dcm but the added jitter is considerable.
Since I am a newbie when it comes to this time stuff, no doubt there will be plenty of you that have more experience with implementations of counters ... so what are regular pitfalls I should be aware of?
Thank you for your time,
Fred
DL
Don Latham
Thu, Jan 6, 2011 7:34 PM
Hi Fred: prescalers in convenient package for experimentation at RFBay.
SMA connectors, though.
Don
Tijd Dingen
To whom it may concerns,
Currently I am building a DIY frequency counter. Since this is my first
serious counter project I am trying to keep things simple, hence It Will
Not Be State Of The Art. Maybe a not-too-difficult hobby level counter
will be of interest to some, so I'd thought I'd post here...
The architecture in a couple of bulletpoints:
- fpga based as much as possible to keep the parts count down
- coarse counters running at max 200 MHz for now
- interpolation is done using TDC's. The TDC's look suspiciously much like
tapped delay lines and are implemented inside the fpga, using mainly the
carry chains.
- 10000 continuous time stamps per second
- 500 ps timestamp resolution. And with resolution I mean the smallest
resolvable thingy (related to bin size), not precision nor accuracy.
That 500 ps is conservative. I intend to do better than that, but just to
give some idea of the starting point... The main thing for now is to get a
handle on the DNL of the TDC.
I am currently playing around with some designs in a spartan-6 and a
spartan-3e. The spartan-6 design has more promise resolution wise, but it
is also not very hobby friendly (bga package). So if this is ever to be
built using hobby level soldering skills it will be spartan-3e. The 250k
gates devices are available in tqfp-100 package which is doable IMO.
The timestamps are transmitted over usb to the pc for number crunching.
The idea is to do some curve fitting to get a frequency estimate,
computate Allan Deviation, and do the obligatory plots. With regard to
Allan Deviation, as long as I make sure the measurements have zero dead
time, I can compute Allan Deviation using the raw time stamps, right?
Also note the glaring lack of a prescaler. This can and will be added at a
later date to extend the range of the counter. For now I just want to get
the basics working properly first. On the subject of prescalers, does
anyone know where to order Hittite parts in low quantities? I noticed on
hittite.com you can place an order but if I understand correctly that is
only for 10+. Which is probably great if you do a group buy, but not if I
want to try out 3 of those, 2 of those, etc...
Another question for those that have already done this ... suppose you
have a "good" 10 MHz (OCXO, GPSDO, WhateverO) and want to use that for
your reference counter. What is a reasonable low cost method to end up
with a 200 MHz clock in a spartan-3e and a 500 MHz clock in a spartan-6? I
am currently using the fpga's internal dcm but the added jitter is
considerable.
Since I am a newbie when it comes to this time stuff, no doubt there will
be plenty of you that have more experience with implementations of
counters ... so what are regular pitfalls I should be aware of?
Thank you for your time,
Fred
time-nuts mailing list -- time-nuts@febo.com
To unsubscribe, go to
https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts
and follow the instructions there.
--
"Neither the voice of authority nor the weight of reason and argument are
as significant as experiment, for thence comes quiet to the mind."
R. Bacon
"If you don't know what it is, don't poke it."
Ghost in the Shell
Dr. Don Latham AJ7LL
Six Mile Systems LLP
17850 Six Mile Road
POB 134
Huson, MT, 59846
VOX 406-626-4304
www.lightningforensics.com
www.sixmilesystems.com
Hi Fred: prescalers in convenient package for experimentation at RFBay.
SMA connectors, though.
Don
Tijd Dingen
> To whom it may concerns,
>
> Currently I am building a DIY frequency counter. Since this is my first
> serious counter project I am trying to keep things simple, hence It Will
> Not Be State Of The Art. Maybe a not-too-difficult hobby level counter
> will be of interest to some, so I'd thought I'd post here...
>
> The architecture in a couple of bulletpoints:
> - fpga based as much as possible to keep the parts count down
> - coarse counters running at max 200 MHz for now
> - interpolation is done using TDC's. The TDC's look suspiciously much like
> tapped delay lines and are implemented inside the fpga, using mainly the
> carry chains.
> - 10000 continuous time stamps per second
> - 500 ps timestamp resolution. And with resolution I mean the smallest
> resolvable thingy (related to bin size), not precision nor accuracy.
>
> That 500 ps is conservative. I intend to do better than that, but just to
> give some idea of the starting point... The main thing for now is to get a
> handle on the DNL of the TDC.
>
> I am currently playing around with some designs in a spartan-6 and a
> spartan-3e. The spartan-6 design has more promise resolution wise, but it
> is also not very hobby friendly (bga package). So if this is ever to be
> built using hobby level soldering skills it will be spartan-3e. The 250k
> gates devices are available in tqfp-100 package which is doable IMO.
>
> The timestamps are transmitted over usb to the pc for number crunching.
> The idea is to do some curve fitting to get a frequency estimate,
> computate Allan Deviation, and do the obligatory plots. With regard to
> Allan Deviation, as long as I make sure the measurements have zero dead
> time, I can compute Allan Deviation using the raw time stamps, right?
>
> Also note the glaring lack of a prescaler. This can and will be added at a
> later date to extend the range of the counter. For now I just want to get
> the basics working properly first. On the subject of prescalers, does
> anyone know where to order Hittite parts in low quantities? I noticed on
> hittite.com you can place an order but if I understand correctly that is
> only for 10+. Which is probably great if you do a group buy, but not if I
> want to try out 3 of those, 2 of those, etc...
>
> Another question for those that have already done this ... suppose you
> have a "good" 10 MHz (OCXO, GPSDO, WhateverO) and want to use that for
> your reference counter. What is a reasonable low cost method to end up
> with a 200 MHz clock in a spartan-3e and a 500 MHz clock in a spartan-6? I
> am currently using the fpga's internal dcm but the added jitter is
> considerable.
>
> Since I am a newbie when it comes to this time stuff, no doubt there will
> be plenty of you that have more experience with implementations of
> counters ... so what are regular pitfalls I should be aware of?
>
> Thank you for your time,
> Fred
>
>
>
>
> _______________________________________________
> time-nuts mailing list -- time-nuts@febo.com
> To unsubscribe, go to
> https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts
> and follow the instructions there.
>
--
"Neither the voice of authority nor the weight of reason and argument are
as significant as experiment, for thence comes quiet to the mind."
R. Bacon
"If you don't know what it is, don't poke it."
Ghost in the Shell
Dr. Don Latham AJ7LL
Six Mile Systems LLP
17850 Six Mile Road
POB 134
Huson, MT, 59846
VOX 406-626-4304
www.lightningforensics.com
www.sixmilesystems.com
S
shalimr9@gmail.com
Thu, Jan 6, 2011 8:25 PM
Fred,
Good luck on your project, it sounds exciting.
I have been able to get a couple of samples for free from Hitite. That was several years ago (before the recession...)
Regarding FPGA, Actel has a demo board for their SmartFusion device (big flash-based FPGA + Cortex M3 processor + 256k program flash separate from the FPGA on the same chip, not a soft core) which has USB slave and Ethernet ports for about $200 in qty 1. There is also a smaller FPGA (ProASIC+) on the board, not sure what it is used for? I have one of these boards, but I have not done anything with it yet. It is a nice board full of potential... The chip is in a BGA package, but if you use this board, you don't need to add much, just the clock and input circuits.
Didier KO4BB
Sent from my Verizon Wireless BlackBerry
-----Original Message-----
From: Tijd Dingen tijddingen@yahoo.com
Sender: time-nuts-bounces@febo.com
Date: Thu, 6 Jan 2011 11:02:12
To: time-nuts@febo.com
Reply-To: Discussion of precise time and frequency measurement
time-nuts@febo.com
Subject: [time-nuts] No State Of The Art Counter
To whom it may concerns,
Currently I am building a DIY frequency counter. Since this is my first serious counter project I am trying to keep things simple, hence It Will Not Be State Of The Art. Maybe a not-too-difficult hobby level counter will be of interest to some, so I'd thought I'd post here...
The architecture in a couple of bulletpoints:
- fpga based as much as possible to keep the parts count down
- coarse counters running at max 200 MHz for now
- interpolation is done using TDC's. The TDC's look suspiciously much like tapped delay lines and are implemented inside the fpga, using mainly the carry chains.
- 10000 continuous time stamps per second
- 500 ps timestamp resolution. And with resolution I mean the smallest resolvable thingy (related to bin size), not precision nor accuracy.
That 500 ps is conservative. I intend to do better than that, but just to give some idea of the starting point... The main thing for now is to get a handle on the DNL of the TDC.
I am currently playing around with some designs in a spartan-6 and a spartan-3e. The spartan-6 design has more promise resolution wise, but it is also not very hobby friendly (bga package). So if this is ever to be built using hobby level soldering skills it will be spartan-3e. The 250k gates devices are available in tqfp-100 package which is doable IMO.
The timestamps are transmitted over usb to the pc for number crunching. The idea is to do some curve fitting to get a frequency estimate, computate Allan Deviation, and do the obligatory plots. With regard to Allan Deviation, as long as I make sure the measurements have zero dead time, I can compute Allan Deviation using the raw time stamps, right?
Also note the glaring lack of a prescaler. This can and will be added at a later date to extend the range of the counter. For now I just want to get the basics working properly first. On the subject of prescalers, does anyone know where to order Hittite parts in low quantities? I noticed on hittite.com you can place an order but if I understand correctly that is only for 10+. Which is probably great if you do a group buy, but not if I want to try out 3 of those, 2 of those, etc...
Another question for those that have already done this ... suppose you have a "good" 10 MHz (OCXO, GPSDO, WhateverO) and want to use that for your reference counter. What is a reasonable low cost method to end up with a 200 MHz clock in a spartan-3e and a 500 MHz clock in a spartan-6? I am currently using the fpga's internal dcm but the added jitter is considerable.
Since I am a newbie when it comes to this time stuff, no doubt there will be plenty of you that have more experience with implementations of counters ... so what are regular pitfalls I should be aware of?
Thank you for your time,
Fred
time-nuts mailing list -- time-nuts@febo.com
To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts
and follow the instructions there.
Fred,
Good luck on your project, it sounds exciting.
I have been able to get a couple of samples for free from Hitite. That was several years ago (before the recession...)
Regarding FPGA, Actel has a demo board for their SmartFusion device (big flash-based FPGA + Cortex M3 processor + 256k program flash separate from the FPGA on the same chip, not a soft core) which has USB slave and Ethernet ports for about $200 in qty 1. There is also a smaller FPGA (ProASIC+) on the board, not sure what it is used for? I have one of these boards, but I have not done anything with it yet. It is a nice board full of potential... The chip is in a BGA package, but if you use this board, you don't need to add much, just the clock and input circuits.
Didier KO4BB
Sent from my Verizon Wireless BlackBerry
-----Original Message-----
From: Tijd Dingen <tijddingen@yahoo.com>
Sender: time-nuts-bounces@febo.com
Date: Thu, 6 Jan 2011 11:02:12
To: <time-nuts@febo.com>
Reply-To: Discussion of precise time and frequency measurement
<time-nuts@febo.com>
Subject: [time-nuts] No State Of The Art Counter
To whom it may concerns,
Currently I am building a DIY frequency counter. Since this is my first serious counter project I am trying to keep things simple, hence It Will Not Be State Of The Art. Maybe a not-too-difficult hobby level counter will be of interest to some, so I'd thought I'd post here...
The architecture in a couple of bulletpoints:
- fpga based as much as possible to keep the parts count down
- coarse counters running at max 200 MHz for now
- interpolation is done using TDC's. The TDC's look suspiciously much like tapped delay lines and are implemented inside the fpga, using mainly the carry chains.
- 10000 continuous time stamps per second
- 500 ps timestamp resolution. And with resolution I mean the smallest resolvable thingy (related to bin size), not precision nor accuracy.
That 500 ps is conservative. I intend to do better than that, but just to give some idea of the starting point... The main thing for now is to get a handle on the DNL of the TDC.
I am currently playing around with some designs in a spartan-6 and a spartan-3e. The spartan-6 design has more promise resolution wise, but it is also not very hobby friendly (bga package). So if this is ever to be built using hobby level soldering skills it will be spartan-3e. The 250k gates devices are available in tqfp-100 package which is doable IMO.
The timestamps are transmitted over usb to the pc for number crunching. The idea is to do some curve fitting to get a frequency estimate, computate Allan Deviation, and do the obligatory plots. With regard to Allan Deviation, as long as I make sure the measurements have zero dead time, I can compute Allan Deviation using the raw time stamps, right?
Also note the glaring lack of a prescaler. This can and will be added at a later date to extend the range of the counter. For now I just want to get the basics working properly first. On the subject of prescalers, does anyone know where to order Hittite parts in low quantities? I noticed on hittite.com you can place an order but if I understand correctly that is only for 10+. Which is probably great if you do a group buy, but not if I want to try out 3 of those, 2 of those, etc...
Another question for those that have already done this ... suppose you have a "good" 10 MHz (OCXO, GPSDO, WhateverO) and want to use that for your reference counter. What is a reasonable low cost method to end up with a 200 MHz clock in a spartan-3e and a 500 MHz clock in a spartan-6? I am currently using the fpga's internal dcm but the added jitter is considerable.
Since I am a newbie when it comes to this time stuff, no doubt there will be plenty of you that have more experience with implementations of counters ... so what are regular pitfalls I should be aware of?
Thank you for your time,
Fred
_______________________________________________
time-nuts mailing list -- time-nuts@febo.com
To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts
and follow the instructions there.
GH
Gerhard Hoffmann
Thu, Jan 6, 2011 9:45 PM
Am 06.01.2011 20:02, schrieb Tijd Dingen:
Also note the glaring lack of a prescaler. This can and will be added at a later date to extend the range of the counter. For now I just want to get the basics working properly first. On the subject of prescalers, does anyone know where to order Hittite parts in low quantities? I noticed on hittite.com you can place an order but if I understand correctly that is only for 10+. Which is probably great if you do a group buy, but not if I want to try out 3 of those, 2 of those, etc...
I was thinking about abusing the built-in SERDES-Units in the Spartan6
as a prescaler. It would
be necessary to sort out the transitions after the 1:16 gearbox, but
given the amount of logic in a Spartan6
that should be possible. While I have not seriously tried that, I have
spotted no show stopper
in the data sheet.
The SERDES units are used for PCI-express, USB3 or fiber optic links
otherwise.
It should be possible to reach 3 or 4 GHz.
Another question for those that have already done this ... suppose you have a "good" 10 MHz (OCXO, GPSDO, WhateverO) and want to use that for your reference counter. What is a reasonable low cost method to end up with a 200 MHz clock in a spartan-3e and a 500 MHz clock in a spartan-6? I am currently using the fpga's internal dcm but the added jitter is considerable.
I would/will use a 100 MHz VCXO locked to a 10 MHz ref and multiply from
then on. That is less ado
than multiplying from 10 MHz up if you want low wideband PN and low
reference harmonics.
Still looking for nice SAW filters for interesting frequencies to get
repeatable no-tune performance.
There is a nice 400 MHz one from ECS/Digikey but I could not tune it on
the VNA to give
reasonable loss/shape. :-(
The system I'm contemplating is more like a SDR with the new 16 bit
200/250MHz ADC
from Analog Devices on a mezzanine card stacked on a SP605.
Maybe even averaging 4 ADCs to increase the dynamic range.
One idea for the SDR would be to lock a sine from a clean 64 bit NCO :-) to
a received carrier in a tight PLL and directly demodulate/measure phase
noise or ADEV
There are so many interesting things one could do w/o a daytime job.
While I'm at it:
I have written a technology-independend sine table and a DDS in VHDL.
I.E. no XBLOX or other silicon vendor stuff that compiles nicely to
block rams and adders/muxes
for Spartan6.
It is estimated by the ISE tools to run at 245 MHz for 16 bit phase and
18 bit amplitude resolution
for sin and cos.
Assumed, there is an ideal clock that goes into a numeric oscillator:
Is there a formula or algorithm that gives guaranteed phase noise / spurs
for the generated sine wave @ arbitrary frequencies, phase- and amplitude
resolution?
regards, Gerhard
Am 06.01.2011 20:02, schrieb Tijd Dingen:
> Also note the glaring lack of a prescaler. This can and will be added at a later date to extend the range of the counter. For now I just want to get the basics working properly first. On the subject of prescalers, does anyone know where to order Hittite parts in low quantities? I noticed on hittite.com you can place an order but if I understand correctly that is only for 10+. Which is probably great if you do a group buy, but not if I want to try out 3 of those, 2 of those, etc...
I was thinking about abusing the built-in SERDES-Units in the Spartan6
as a prescaler. It would
be necessary to sort out the transitions after the 1:16 gearbox, but
given the amount of logic in a Spartan6
that should be possible. While I have not seriously tried that, I have
spotted no show stopper
in the data sheet.
The SERDES units are used for PCI-express, USB3 or fiber optic links
otherwise.
It should be possible to reach 3 or 4 GHz.
> Another question for those that have already done this ... suppose you have a "good" 10 MHz (OCXO, GPSDO, WhateverO) and want to use that for your reference counter. What is a reasonable low cost method to end up with a 200 MHz clock in a spartan-3e and a 500 MHz clock in a spartan-6? I am currently using the fpga's internal dcm but the added jitter is considerable.
I would/will use a 100 MHz VCXO locked to a 10 MHz ref and multiply from
then on. That is less ado
than multiplying from 10 MHz up if you want low wideband PN and low
reference harmonics.
Still looking for nice SAW filters for interesting frequencies to get
repeatable no-tune performance.
There is a nice 400 MHz one from ECS/Digikey but I could not tune it on
the VNA to give
reasonable loss/shape. :-(
The system I'm contemplating is more like a SDR with the new 16 bit
200/250MHz ADC
from Analog Devices on a mezzanine card stacked on a SP605.
Maybe even averaging 4 ADCs to increase the dynamic range.
One idea for the SDR would be to lock a sine from a clean 64 bit NCO :-) to
a received carrier in a tight PLL and directly demodulate/measure phase
noise or ADEV
There are so many interesting things one could do w/o a daytime job.
While I'm at it:
I have written a technology-independend sine table and a DDS in VHDL.
I.E. no XBLOX or other silicon vendor stuff that compiles nicely to
block rams and adders/muxes
for Spartan6.
It is estimated by the ISE tools to run at 245 MHz for 16 bit phase and
18 bit amplitude resolution
for sin and cos.
Assumed, there is an ideal clock that goes into a numeric oscillator:
Is there a formula or algorithm that gives guaranteed phase noise / spurs
for the generated sine wave @ arbitrary frequencies, phase- and amplitude
resolution?
regards, Gerhard
TD
Tijd Dingen
Thu, Jan 6, 2011 9:53 PM
Didier,
Thanks. I doubt Hittite will send me a couple of samples for "this one and
that one and oh that one", but you do raise a good point. I can always try! :)
With respect to fpga development boards, for this project I am all set! I am
currently tinkering with these two boards:
http://www.digilentinc.com/Products/Detail.cfm?Prod=NEXYS2
http://www.digilentinc.com/Products/Detail.cfm?Prod=ATLYS
Both have one of those ez-usb fx2 controllers from cypress (cy7c68013a),
which I find easy to work with under linux. Plus I already had verilog
modules from some older projects that take care of the usb fifos on the fpga
side.
As for processor, currently I use a picoblaze softcore which works for both
the spartan-3 and spartan-6. So I only have to write code for that once...
My remarks regarding the tqpf-100 package was for the benefit of those who
might be looking for something to put in a DIY counter and want to be able
to solder it themselves. Since I'm already using these development boards
for other stuff as well, I thought it would be fun to see how far one can
take these things timing resolution-wise...
I am not familiar with the Actel parts. Do you happen to know what kind of
timing granularity is possible with the carry chain or similar structures on
those Actels?
regards,
Fred
--- On Thu, 1/6/11, shalimr9@gmail.com shalimr9@gmail.com wrote:
From: shalimr9@gmail.com shalimr9@gmail.com
Subject: Re: [time-nuts] No State Of The Art Counter
To: "Time-Nuts" time-nuts@febo.com
Date: Thursday, January 6, 2011, 8:25 PM
Fred,
Good luck on your project, it sounds exciting.
I have been able to get a couple of samples for free from
Hitite. That was several years ago (before the
recession...)
Regarding FPGA, Actel has a demo board for their
SmartFusion device (big flash-based FPGA + Cortex M3
processor + 256k program flash separate from the FPGA on the
same chip, not a soft core) which has USB slave and Ethernet
ports for about $200 in qty 1. There is also a smaller FPGA
(ProASIC+) on the board, not sure what it is used for? I
have one of these boards, but I have not done anything with
it yet. It is a nice board full of potential... The chip is
in a BGA package, but if you use this board, you don't need
to add much, just the clock and input circuits.
Didier KO4BB
Sent from my Verizon Wireless BlackBerry
-----Original Message-----
From: Tijd Dingen tijddingen@yahoo.com
Sender: time-nuts-bounces@febo.com
Date: Thu, 6 Jan 2011 11:02:12
To: time-nuts@febo.com
Reply-To: Discussion of precise time and frequency
measurement
time-nuts@febo.com
Subject: [time-nuts] No State Of The Art Counter
To whom it may concerns,
Currently I am building a DIY frequency counter. Since this
is my first serious counter project I am trying to keep
things simple, hence It Will Not Be State Of The Art. Maybe
a not-too-difficult hobby level counter will be of interest
to some, so I'd thought I'd post here...
The architecture in a couple of bulletpoints:
- fpga based as much as possible to keep the parts count
down
- coarse counters running at max 200 MHz for now
- interpolation is done using TDC's. The TDC's look
suspiciously much like tapped delay lines and are
implemented inside the fpga, using mainly the carry chains.
- 10000 continuous time stamps per second
- 500 ps timestamp resolution. And with resolution I mean
the smallest resolvable thingy (related to bin size), not
precision nor accuracy.
That 500 ps is conservative. I intend to do better than
that, but just to give some idea of the starting point...
The main thing for now is to get a handle on the DNL of the
TDC.
I am currently playing around with some designs in a
spartan-6 and a spartan-3e. The spartan-6 design has more
promise resolution wise, but it is also not very hobby
friendly (bga package). So if this is ever to be built using
hobby level soldering skills it will be spartan-3e. The 250k
gates devices are available in tqfp-100 package which is
doable IMO.
The timestamps are transmitted over usb to the pc for
number crunching. The idea is to do some curve fitting to
get a frequency estimate, computate Allan Deviation, and do
the obligatory plots. With regard to Allan Deviation, as
long as I make sure the measurements have zero dead time, I
can compute Allan Deviation using the raw time stamps,
right?
Also note the glaring lack of a prescaler. This can and
will be added at a later date to extend the range of the
counter. For now I just want to get the basics working
properly first. On the subject of prescalers, does anyone
know where to order Hittite parts in low quantities? I
noticed on hittite.com you can place an order but if I
understand correctly that is only for 10+. Which is probably
great if you do a group buy, but not if I want to try out 3
of those, 2 of those, etc...
Another question for those that have already done this ...
suppose you have a "good" 10 MHz (OCXO, GPSDO, WhateverO)
and want to use that for your reference counter. What is a
reasonable low cost method to end up with a 200 MHz clock in
a spartan-3e and a 500 MHz clock in a spartan-6? I am
currently using the fpga's internal dcm but the added jitter
is considerable.
Since I am a newbie when it comes to this time stuff, no
doubt there will be plenty of you that have more experience
with implementations of counters ... so what are regular
pitfalls I should be aware of?
Thank you for your time,
Fred
time-nuts mailing list -- time-nuts@febo.com
To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts
and follow the instructions there.
time-nuts mailing list -- time-nuts@febo.com
To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts
and follow the instructions there.
Didier,
Thanks. I doubt Hittite will send me a couple of samples for "this one and
that one and oh that one", but you do raise a good point. I can always try! :)
With respect to fpga development boards, for this project I am all set! I am
currently tinkering with these two boards:
http://www.digilentinc.com/Products/Detail.cfm?Prod=NEXYS2
http://www.digilentinc.com/Products/Detail.cfm?Prod=ATLYS
Both have one of those ez-usb fx2 controllers from cypress (cy7c68013a),
which I find easy to work with under linux. Plus I already had verilog
modules from some older projects that take care of the usb fifos on the fpga
side.
As for processor, currently I use a picoblaze softcore which works for both
the spartan-3 and spartan-6. So I only have to write code for that once...
My remarks regarding the tqpf-100 package was for the benefit of those who
might be looking for something to put in a DIY counter and want to be able
to solder it themselves. Since I'm already using these development boards
for other stuff as well, I thought it would be fun to see how far one can
take these things timing resolution-wise...
I am not familiar with the Actel parts. Do you happen to know what kind of
timing granularity is possible with the carry chain or similar structures on
those Actels?
regards,
Fred
--- On Thu, 1/6/11, shalimr9@gmail.com <shalimr9@gmail.com> wrote:
> From: shalimr9@gmail.com <shalimr9@gmail.com>
> Subject: Re: [time-nuts] No State Of The Art Counter
> To: "Time-Nuts" <time-nuts@febo.com>
> Date: Thursday, January 6, 2011, 8:25 PM
> Fred,
>
> Good luck on your project, it sounds exciting.
>
> I have been able to get a couple of samples for free from
> Hitite. That was several years ago (before the
> recession...)
>
> Regarding FPGA, Actel has a demo board for their
> SmartFusion device (big flash-based FPGA + Cortex M3
> processor + 256k program flash separate from the FPGA on the
> same chip, not a soft core) which has USB slave and Ethernet
> ports for about $200 in qty 1. There is also a smaller FPGA
> (ProASIC+) on the board, not sure what it is used for? I
> have one of these boards, but I have not done anything with
> it yet. It is a nice board full of potential... The chip is
> in a BGA package, but if you use this board, you don't need
> to add much, just the clock and input circuits.
>
> Didier KO4BB
>
> Sent from my Verizon Wireless BlackBerry
>
> -----Original Message-----
> From: Tijd Dingen <tijddingen@yahoo.com>
> Sender: time-nuts-bounces@febo.com
> Date: Thu, 6 Jan 2011 11:02:12
> To: <time-nuts@febo.com>
> Reply-To: Discussion of precise time and frequency
> measurement
> <time-nuts@febo.com>
> Subject: [time-nuts] No State Of The Art Counter
>
> To whom it may concerns,
>
> Currently I am building a DIY frequency counter. Since this
> is my first serious counter project I am trying to keep
> things simple, hence It Will Not Be State Of The Art. Maybe
> a not-too-difficult hobby level counter will be of interest
> to some, so I'd thought I'd post here...
>
> The architecture in a couple of bulletpoints:
> - fpga based as much as possible to keep the parts count
> down
> - coarse counters running at max 200 MHz for now
> - interpolation is done using TDC's. The TDC's look
> suspiciously much like tapped delay lines and are
> implemented inside the fpga, using mainly the carry chains.
> - 10000 continuous time stamps per second
> - 500 ps timestamp resolution. And with resolution I mean
> the smallest resolvable thingy (related to bin size), not
> precision nor accuracy.
>
> That 500 ps is conservative. I intend to do better than
> that, but just to give some idea of the starting point...
> The main thing for now is to get a handle on the DNL of the
> TDC.
>
> I am currently playing around with some designs in a
> spartan-6 and a spartan-3e. The spartan-6 design has more
> promise resolution wise, but it is also not very hobby
> friendly (bga package). So if this is ever to be built using
> hobby level soldering skills it will be spartan-3e. The 250k
> gates devices are available in tqfp-100 package which is
> doable IMO.
>
> The timestamps are transmitted over usb to the pc for
> number crunching. The idea is to do some curve fitting to
> get a frequency estimate, computate Allan Deviation, and do
> the obligatory plots. With regard to Allan Deviation, as
> long as I make sure the measurements have zero dead time, I
> can compute Allan Deviation using the raw time stamps,
> right?
>
> Also note the glaring lack of a prescaler. This can and
> will be added at a later date to extend the range of the
> counter. For now I just want to get the basics working
> properly first. On the subject of prescalers, does anyone
> know where to order Hittite parts in low quantities? I
> noticed on hittite.com you can place an order but if I
> understand correctly that is only for 10+. Which is probably
> great if you do a group buy, but not if I want to try out 3
> of those, 2 of those, etc...
>
> Another question for those that have already done this ...
> suppose you have a "good" 10 MHz (OCXO, GPSDO, WhateverO)
> and want to use that for your reference counter. What is a
> reasonable low cost method to end up with a 200 MHz clock in
> a spartan-3e and a 500 MHz clock in a spartan-6? I am
> currently using the fpga's internal dcm but the added jitter
> is considerable.
>
> Since I am a newbie when it comes to this time stuff, no
> doubt there will be plenty of you that have more experience
> with implementations of counters ... so what are regular
> pitfalls I should be aware of?
>
> Thank you for your time,
> Fred
>
>
>
>
> _______________________________________________
> time-nuts mailing list -- time-nuts@febo.com
> To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts
> and follow the instructions there.
> _______________________________________________
> time-nuts mailing list -- time-nuts@febo.com
> To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts
> and follow the instructions there.
>
MD
Magnus Danielson
Thu, Jan 6, 2011 10:05 PM
On 01/06/2011 08:02 PM, Tijd Dingen wrote:
To whom it may concerns,
Currently I am building a DIY frequency counter. Since this is my first serious counter project I am trying to keep things simple, hence It Will Not Be State Of The Art. Maybe a not-too-difficult hobby level counter will be of interest to some, so I'd thought I'd post here...
The architecture in a couple of bulletpoints:
- fpga based as much as possible to keep the parts count down
- coarse counters running at max 200 MHz for now
- interpolation is done using TDC's. The TDC's look suspiciously much like tapped delay lines and are implemented inside the fpga, using mainly the carry chains.
- 10000 continuous time stamps per second
- 500 ps timestamp resolution. And with resolution I mean the smallest resolvable thingy (related to bin size), not precision nor accuracy.
500 ps single-shot resolution is what you probably want to say.
How will the input side work? How will you handle input signals of
various kinds? In particular sine of various amplitudes and frequencies.
Slew-rate can be a limiting factor as white noise will convert into
jitter if hitting a straight comparator. Choice of trigger point can be
done to achieve lowest jitter, so just AC-blocking and trigger on the 0V
may not be the best solution if shape is not well known. Noise of input
stage comes into play.
That 500 ps is conservative. I intend to do better than that, but just to give some idea of the starting point... The main thing for now is to get a handle on the DNL of the TDC.
I am currently playing around with some designs in a spartan-6 and a spartan-3e. The spartan-6 design has more promise resolution wise, but it is also not very hobby friendly (bga package). So if this is ever to be built using hobby level soldering skills it will be spartan-3e. The 250k gates devices are available in tqfp-100 package which is doable IMO.
BGAs solder with hot-air gun and correct use of fluss.
The timestamps are transmitted over usb to the pc for number crunching. The idea is to do some curve fitting to get a frequency estimate, computate Allan Deviation, and do the obligatory plots. With regard to Allan Deviation, as long as I make sure the measurements have zero dead time, I can compute Allan Deviation using the raw time stamps, right?
Yes. Make sure time-stamps has a format such that software can do
time-wrapping extension.
Cheers,
Magnus
On 01/06/2011 08:02 PM, Tijd Dingen wrote:
> To whom it may concerns,
>
> Currently I am building a DIY frequency counter. Since this is my first serious counter project I am trying to keep things simple, hence It Will Not Be State Of The Art. Maybe a not-too-difficult hobby level counter will be of interest to some, so I'd thought I'd post here...
>
> The architecture in a couple of bulletpoints:
> - fpga based as much as possible to keep the parts count down
> - coarse counters running at max 200 MHz for now
> - interpolation is done using TDC's. The TDC's look suspiciously much like tapped delay lines and are implemented inside the fpga, using mainly the carry chains.
> - 10000 continuous time stamps per second
> - 500 ps timestamp resolution. And with resolution I mean the smallest resolvable thingy (related to bin size), not precision nor accuracy.
500 ps single-shot resolution is what you probably want to say.
How will the input side work? How will you handle input signals of
various kinds? In particular sine of various amplitudes and frequencies.
Slew-rate can be a limiting factor as white noise will convert into
jitter if hitting a straight comparator. Choice of trigger point can be
done to achieve lowest jitter, so just AC-blocking and trigger on the 0V
may not be the best solution if shape is not well known. Noise of input
stage comes into play.
> That 500 ps is conservative. I intend to do better than that, but just to give some idea of the starting point... The main thing for now is to get a handle on the DNL of the TDC.
>
> I am currently playing around with some designs in a spartan-6 and a spartan-3e. The spartan-6 design has more promise resolution wise, but it is also not very hobby friendly (bga package). So if this is ever to be built using hobby level soldering skills it will be spartan-3e. The 250k gates devices are available in tqfp-100 package which is doable IMO.
BGAs solder with hot-air gun and correct use of fluss.
> The timestamps are transmitted over usb to the pc for number crunching. The idea is to do some curve fitting to get a frequency estimate, computate Allan Deviation, and do the obligatory plots. With regard to Allan Deviation, as long as I make sure the measurements have zero dead time, I can compute Allan Deviation using the raw time stamps, right?
Yes. Make sure time-stamps has a format such that software can do
time-wrapping extension.
Cheers,
Magnus
GH
Gerhard Hoffmann
Thu, Jan 6, 2011 10:54 PM
Am 06.01.2011 22:45, schrieb Gerhard Hoffmann:
I was thinking about abusing the built-in SERDES-Units in the Spartan6
as a prescaler. It would
be necessary to sort out the transitions after the 1:16 gearbox, but
given the amount of logic in a Spartan6
that should be possible. While I have not seriously tried that, I have
spotted no show stopper
in the data sheet.
The SERDES units are used for PCI-express, USB3 or fiber optic links
otherwise.
It should be possible to reach 3 or 4 GHz.
To clarify this:
That would not be a prescaler but a full range extension.
Timestamping would be possible at 3 or 4 GHz.
And I meant SATA-3, not USB3.
Gerhard
Am 06.01.2011 22:45, schrieb Gerhard Hoffmann:
> I was thinking about abusing the built-in SERDES-Units in the Spartan6
> as a prescaler. It would
> be necessary to sort out the transitions after the 1:16 gearbox, but
> given the amount of logic in a Spartan6
> that should be possible. While I have not seriously tried that, I have
> spotted no show stopper
> in the data sheet.
> The SERDES units are used for PCI-express, USB3 or fiber optic links
> otherwise.
> It should be possible to reach 3 or 4 GHz.
>
To clarify this:
That would not be a prescaler but a full range extension.
Timestamping would be possible at 3 or 4 GHz.
And I meant SATA-3, not USB3.
Gerhard
MD
Magnus Danielson
Thu, Jan 6, 2011 11:24 PM
On 01/06/2011 11:54 PM, Gerhard Hoffmann wrote:
Am 06.01.2011 22:45, schrieb Gerhard Hoffmann:
I was thinking about abusing the built-in SERDES-Units in the Spartan6
as a prescaler. It would
be necessary to sort out the transitions after the 1:16 gearbox, but
given the amount of logic in a Spartan6
that should be possible. While I have not seriously tried that, I have
spotted no show stopper
in the data sheet.
The SERDES units are used for PCI-express, USB3 or fiber optic links
otherwise.
It should be possible to reach 3 or 4 GHz.
To clarify this:
That would not be a prescaler but a full range extension.
Timestamping would be possible at 3 or 4 GHz.
And I meant SATA-3, not USB3.
For a SERDES to be useable as a high frequency input, the Rx SERDES
needs to be able to use the reference clock as clock source rather than
doing clock recovery. While the SERDESes I have seen is able to do that,
one always want to check that detail before going further into the
design. For reference you typically use a SAW-oscillator which in this
case probably should have a VC input so you can lock it up. Should not
be too hard to find a suitable one.
I've considered this approach myself, but just not got around to cook
something up.
It's a bit of a design-challenge to do a parallel trigger detection and
event counter, but it is doable.
Cheers,
Magnus
On 01/06/2011 11:54 PM, Gerhard Hoffmann wrote:
> Am 06.01.2011 22:45, schrieb Gerhard Hoffmann:
>> I was thinking about abusing the built-in SERDES-Units in the Spartan6
>> as a prescaler. It would
>> be necessary to sort out the transitions after the 1:16 gearbox, but
>> given the amount of logic in a Spartan6
>> that should be possible. While I have not seriously tried that, I have
>> spotted no show stopper
>> in the data sheet.
>> The SERDES units are used for PCI-express, USB3 or fiber optic links
>> otherwise.
>> It should be possible to reach 3 or 4 GHz.
>>
> To clarify this:
>
> That would not be a prescaler but a full range extension.
> Timestamping would be possible at 3 or 4 GHz.
>
> And I meant SATA-3, not USB3.
For a SERDES to be useable as a high frequency input, the Rx SERDES
needs to be able to use the reference clock as clock source rather than
doing clock recovery. While the SERDESes I have seen is able to do that,
one always want to check that detail before going further into the
design. For reference you typically use a SAW-oscillator which in this
case probably should have a VC input so you can lock it up. Should not
be too hard to find a suitable one.
I've considered this approach myself, but just not got around to cook
something up.
It's a bit of a design-challenge to do a parallel trigger detection and
event counter, but it is doable.
Cheers,
Magnus
GH
Gerhard Hoffmann
Thu, Jan 6, 2011 11:42 PM
Am 07.01.2011 00:24, schrieb Magnus Danielson:
For a SERDES to be useable as a high frequency input, the Rx SERDES
needs to be able to use the reference clock as clock source rather
than doing clock recovery. While the SERDESes I have seen is able to
do that, one always want to check that detail before going further
into the design. For reference you typically use a SAW-oscillator
which in this case probably should have a VC input so you can lock it
up. Should not be too hard to find a suitable one.
On The SP605 board, you can inject the clock via 1 or 2 SMAs, single
ended or differential
I've considered this approach myself, but just not got around to cook
something up.
It's a bit of a design-challenge to do a parallel trigger detection
and event counter, but it is doable.
Yes.
If you look at the input signal as a 4 GB/s bit stream, you get it
served as a 16 or 32 bit wide stream
at 1/16 or 1/32 the rate. Recognizing the 0->1 and 1->0 transitions may
need some pipeline stages
and some work, but it is not really difficult.
The time stamp is simply the serial number of the 16/32 bit word and the
location of the bit that flips.
Plowing with the power of a thousand chicken.
Gerhard :-)
Am 07.01.2011 00:24, schrieb Magnus Danielson:
>
> For a SERDES to be useable as a high frequency input, the Rx SERDES
> needs to be able to use the reference clock as clock source rather
> than doing clock recovery. While the SERDESes I have seen is able to
> do that, one always want to check that detail before going further
> into the design. For reference you typically use a SAW-oscillator
> which in this case probably should have a VC input so you can lock it
> up. Should not be too hard to find a suitable one.
>
On The SP605 board, you can inject the clock via 1 or 2 SMAs, single
ended or differential
> I've considered this approach myself, but just not got around to cook
> something up.
>
> It's a bit of a design-challenge to do a parallel trigger detection
> and event counter, but it is doable.
Yes.
If you look at the input signal as a 4 GB/s bit stream, you get it
served as a 16 or 32 bit wide stream
at 1/16 or 1/32 the rate. Recognizing the 0->1 and 1->0 transitions may
need some pipeline stages
and some work, but it is not really difficult.
The time stamp is simply the serial number of the 16/32 bit word and the
location of the bit that flips.
Plowing with the power of a thousand chicken.
Gerhard :-)
MD
Magnus Danielson
Thu, Jan 6, 2011 11:57 PM
On 01/07/2011 12:42 AM, Gerhard Hoffmann wrote:
Am 07.01.2011 00:24, schrieb Magnus Danielson:
For a SERDES to be useable as a high frequency input, the Rx SERDES
needs to be able to use the reference clock as clock source rather
than doing clock recovery. While the SERDESes I have seen is able to
do that, one always want to check that detail before going further
into the design. For reference you typically use a SAW-oscillator
which in this case probably should have a VC input so you can lock it
up. Should not be too hard to find a suitable one.
On The SP605 board, you can inject the clock via 1 or 2 SMAs, single
ended or differential
I've considered this approach myself, but just not got around to cook
something up.
It's a bit of a design-challenge to do a parallel trigger detection
and event counter, but it is doable.
Yes.
If you look at the input signal as a 4 GB/s bit stream, you get it
served as a 16 or 32 bit wide stream
at 1/16 or 1/32 the rate. Recognizing the 0->1 and 1->0 transitions may
need some pipeline stages
and some work, but it is not really difficult.
The time stamp is simply the serial number of the 16/32 bit word and the
location of the bit that flips.
But one has to recall that a 0->1 transition can occur between the
words, and one also has to recall to identify the first 0->1 transition
in such a word with a bit-number indication.
Also, one has to count the number of 0->1 transitions in each word, such
that the event counter can be accumulated with the contribution from
each word.
A convenient approach is to use a tree structure to summaries and
identify things hierarchically. The last bit of the previous word needs
to be known.
For a 16-bit word, 16 rise detections is needed, and 15 early/late
comparators & summers is needed. This architecture can be suitably
pipe-lined to maintain full speed.
If one wants falling detections as well, then just invert the samples or
let the rise-detections also do fall-detection. Goes into one LUT
regardless (three-inputs rather than two inputs).
Cheers,
Magnus
On 01/07/2011 12:42 AM, Gerhard Hoffmann wrote:
> Am 07.01.2011 00:24, schrieb Magnus Danielson:
>>
>> For a SERDES to be useable as a high frequency input, the Rx SERDES
>> needs to be able to use the reference clock as clock source rather
>> than doing clock recovery. While the SERDESes I have seen is able to
>> do that, one always want to check that detail before going further
>> into the design. For reference you typically use a SAW-oscillator
>> which in this case probably should have a VC input so you can lock it
>> up. Should not be too hard to find a suitable one.
>>
> On The SP605 board, you can inject the clock via 1 or 2 SMAs, single
> ended or differential
>
>> I've considered this approach myself, but just not got around to cook
>> something up.
>>
>> It's a bit of a design-challenge to do a parallel trigger detection
>> and event counter, but it is doable.
>
> Yes.
> If you look at the input signal as a 4 GB/s bit stream, you get it
> served as a 16 or 32 bit wide stream
> at 1/16 or 1/32 the rate. Recognizing the 0->1 and 1->0 transitions may
> need some pipeline stages
> and some work, but it is not really difficult.
> The time stamp is simply the serial number of the 16/32 bit word and the
> location of the bit that flips.
But one has to recall that a 0->1 transition can occur between the
words, and one also has to recall to identify the first 0->1 transition
in such a word with a bit-number indication.
Also, one has to count the number of 0->1 transitions in each word, such
that the event counter can be accumulated with the contribution from
each word.
A convenient approach is to use a tree structure to summaries and
identify things hierarchically. The last bit of the previous word needs
to be known.
For a 16-bit word, 16 rise detections is needed, and 15 early/late
comparators & summers is needed. This architecture can be suitably
pipe-lined to maintain full speed.
If one wants falling detections as well, then just invert the samples or
let the rise-detections also do fall-detection. Goes into one LUT
regardless (three-inputs rather than two inputs).
Cheers,
Magnus
JM
John Miles
Fri, Jan 7, 2011 1:35 AM
I am currently playing around with some designs in a spartan-6 and a
spartan-3e. The spartan-6 design has more promise resolution
is also not very hobby friendly (bga package). So if this is ever to be
built using hobby level soldering skills it will be spartan-3e. The 250k
gates devices are available in tqfp-100 package which is doable IMO.
Actually you can even get the XC3S500Es in VQG100 flat-pack packages.
The timestamps are transmitted over usb to the pc for number crunching.
The idea is to do some curve fitting to get a frequency estimate,
computate Allan Deviation, and do the obligatory plots. With regard to
Allan Deviation, as long as I make sure the measurements have zero dead
time, I can compute Allan Deviation using the raw time stamps, right?
Also note the glaring lack of a prescaler. This can and will be
later date to extend the range of the counter. For now I just
the basics working properly first. On the subject of prescalers, does
anyone know where to order Hittite parts in low quantities? I noticed on
hittite.com you can place an order but if I understand correctly that is
only for 10+. Which is probably great if you do a group buy,
want to try out 3 of those, 2 of those, etc...
For prescaling, I'd suggest using the dividers in one of the Analog Devices
PLL parts (ADF4xxx) instead of Hittite chips. Many of the AD parts can
still be purchased in packages with actual pins, and you can always get them
in small quantities. They will also take a lot less power.
You only need to use the Hittite parts if you (a) don't have a controller of
some sort and/or (b) need lower noise or some other spec that the CMOS parts
from AD can't match.
-- john, KE5FX
> > I am currently playing around with some designs in a spartan-6 and a
> > spartan-3e. The spartan-6 design has more promise resolution
> wise, but it
> > is also not very hobby friendly (bga package). So if this is ever to be
> > built using hobby level soldering skills it will be spartan-3e. The 250k
> > gates devices are available in tqfp-100 package which is doable IMO.
Actually you can even get the XC3S500Es in VQG100 flat-pack packages.
> > The timestamps are transmitted over usb to the pc for number crunching.
> > The idea is to do some curve fitting to get a frequency estimate,
> > computate Allan Deviation, and do the obligatory plots. With regard to
> > Allan Deviation, as long as I make sure the measurements have zero dead
> > time, I can compute Allan Deviation using the raw time stamps, right?
Yes.
> > Also note the glaring lack of a prescaler. This can and will be
> added at a
> > later date to extend the range of the counter. For now I just
> want to get
> > the basics working properly first. On the subject of prescalers, does
> > anyone know where to order Hittite parts in low quantities? I noticed on
> > hittite.com you can place an order but if I understand correctly that is
> > only for 10+. Which is probably great if you do a group buy,
> but not if I
> > want to try out 3 of those, 2 of those, etc...
For prescaling, I'd suggest using the dividers in one of the Analog Devices
PLL parts (ADF4xxx) instead of Hittite chips. Many of the AD parts can
still be purchased in packages with actual pins, and you can always get them
in small quantities. They will also take a lot less power.
You only need to use the Hittite parts if you (a) don't have a controller of
some sort and/or (b) need lower noise or some other spec that the CMOS parts
from AD can't match.
-- john, KE5FX
BG
Bruce Griffiths
Fri, Jan 7, 2011 11:28 AM
Am 06.01.2011 20:02, schrieb Tijd Dingen:
Also note the glaring lack of a prescaler. This can and will be added
at a later date to extend the range of the counter. For now I just
want to get the basics working properly first. On the subject of
prescalers, does anyone know where to order Hittite parts in low
quantities? I noticed on hittite.com you can place an order but if I
understand correctly that is only for 10+. Which is probably great if
you do a group buy, but not if I want to try out 3 of those, 2 of
those, etc...
I was thinking about abusing the built-in SERDES-Units in the Spartan6
as a prescaler. It would
be necessary to sort out the transitions after the 1:16 gearbox, but
given the amount of logic in a Spartan6
that should be possible. While I have not seriously tried that, I have
spotted no show stopper
in the data sheet.
The SERDES units are used for PCI-express, USB3 or fiber optic links
otherwise.
It should be possible to reach 3 or 4 GHz.
Another question for those that have already done this ... suppose
you have a "good" 10 MHz (OCXO, GPSDO, WhateverO) and want to use
that for your reference counter. What is a reasonable low cost method
to end up with a 200 MHz clock in a spartan-3e and a 500 MHz clock in
a spartan-6? I am currently using the fpga's internal dcm but the
added jitter is considerable.
I would/will use a 100 MHz VCXO locked to a 10 MHz ref and multiply
from then on. That is less ado
than multiplying from 10 MHz up if you want low wideband PN and low
reference harmonics.
Still looking for nice SAW filters for interesting frequencies to get
repeatable no-tune performance.
There is a nice 400 MHz one from ECS/Digikey but I could not tune it
on the VNA to give
reasonable loss/shape. :-(
The system I'm contemplating is more like a SDR with the new 16 bit
200/250MHz ADC
from Analog Devices on a mezzanine card stacked on a SP605.
Maybe even averaging 4 ADCs to increase the dynamic range.
One idea for the SDR would be to lock a sine from a clean 64 bit NCO
:-) to
a received carrier in a tight PLL and directly demodulate/measure
phase noise or ADEV
There are so many interesting things one could do w/o a daytime job.
While I'm at it:
I have written a technology-independend sine table and a DDS in VHDL.
I.E. no XBLOX or other silicon vendor stuff that compiles nicely to
block rams and adders/muxes
for Spartan6.
It is estimated by the ISE tools to run at 245 MHz for 16 bit phase
and 18 bit amplitude resolution
for sin and cos.
Assumed, there is an ideal clock that goes into a numeric oscillator:
Is there a formula or algorithm that gives guaranteed phase noise / spurs
for the generated sine wave @ arbitrary frequencies, phase- and amplitude
resolution?
regards, Gerhard
time-nuts mailing list -- time-nuts@febo.com
To unsubscribe, go to
https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts
and follow the instructions there.
Gerhard
See:
http://www.sdrforum.org/pages/sdr06/sdr06_papers/1.3/1.3-01.pdf
for an ultra low phase noise dds technique.
Bruce
Gerhard Hoffmann wrote:
> Am 06.01.2011 20:02, schrieb Tijd Dingen:
>> Also note the glaring lack of a prescaler. This can and will be added
>> at a later date to extend the range of the counter. For now I just
>> want to get the basics working properly first. On the subject of
>> prescalers, does anyone know where to order Hittite parts in low
>> quantities? I noticed on hittite.com you can place an order but if I
>> understand correctly that is only for 10+. Which is probably great if
>> you do a group buy, but not if I want to try out 3 of those, 2 of
>> those, etc...
> I was thinking about abusing the built-in SERDES-Units in the Spartan6
> as a prescaler. It would
> be necessary to sort out the transitions after the 1:16 gearbox, but
> given the amount of logic in a Spartan6
> that should be possible. While I have not seriously tried that, I have
> spotted no show stopper
> in the data sheet.
> The SERDES units are used for PCI-express, USB3 or fiber optic links
> otherwise.
> It should be possible to reach 3 or 4 GHz.
>
>> Another question for those that have already done this ... suppose
>> you have a "good" 10 MHz (OCXO, GPSDO, WhateverO) and want to use
>> that for your reference counter. What is a reasonable low cost method
>> to end up with a 200 MHz clock in a spartan-3e and a 500 MHz clock in
>> a spartan-6? I am currently using the fpga's internal dcm but the
>> added jitter is considerable.
> I would/will use a 100 MHz VCXO locked to a 10 MHz ref and multiply
> from then on. That is less ado
> than multiplying from 10 MHz up if you want low wideband PN and low
> reference harmonics.
>
> Still looking for nice SAW filters for interesting frequencies to get
> repeatable no-tune performance.
> There is a nice 400 MHz one from ECS/Digikey but I could not tune it
> on the VNA to give
> reasonable loss/shape. :-(
>
>
> The system I'm contemplating is more like a SDR with the new 16 bit
> 200/250MHz ADC
> from Analog Devices on a mezzanine card stacked on a SP605.
> Maybe even averaging 4 ADCs to increase the dynamic range.
> One idea for the SDR would be to lock a sine from a clean 64 bit NCO
> :-) to
> a received carrier in a tight PLL and directly demodulate/measure
> phase noise or ADEV
>
> There are so many interesting things one could do w/o a daytime job.
>
>
> While I'm at it:
> I have written a technology-independend sine table and a DDS in VHDL.
> I.E. no XBLOX or other silicon vendor stuff that compiles nicely to
> block rams and adders/muxes
> for Spartan6.
> It is estimated by the ISE tools to run at 245 MHz for 16 bit phase
> and 18 bit amplitude resolution
> for sin and cos.
>
> Assumed, there is an ideal clock that goes into a numeric oscillator:
>
> Is there a formula or algorithm that gives guaranteed phase noise / spurs
> for the generated sine wave @ arbitrary frequencies, phase- and amplitude
> resolution?
>
>
> regards, Gerhard
>
>
> _______________________________________________
> time-nuts mailing list -- time-nuts@febo.com
> To unsubscribe, go to
> https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts
> and follow the instructions there.
>
TD
Tijd Dingen
Fri, Jan 7, 2011 10:14 PM
For prescaling, I'd suggest using the dividers in one of the Analog Devices
PLL parts (ADF4xxx) instead of Hittite chips. Many of the AD parts can
still be purchased in packages with actual pins, and you can always get them
in small quantities. They will also take a lot less power.
Then I suppose it's a good thing I already have some adf4106 + adf5001 in the parts box. :)
> For prescaling, I'd suggest using the dividers in one of the Analog Devices
> PLL parts (ADF4xxx) instead of Hittite chips. Many of the AD parts can
> still be purchased in packages with actual pins, and you can always get them
> in small quantities. They will also take a lot less power.
Then I suppose it's a good thing I already have some adf4106 + adf5001 in the parts box. :)
TD
Tijd Dingen
Fri, Jan 7, 2011 10:45 PM
From: Magnus Danielson magnus@rubidium.dyndns.org
Subject: Re: [time-nuts] No State Of The Art Counter
To: "Discussion of precise time and frequency measurement" time-nuts@febo.com
Date: Thursday, January 6, 2011, 10:05 PM
On 01/06/2011 08:02 PM, Tijd Dingen
wrote:
To whom it may concerns,
Currently I am building a DIY frequency counter. Since
this is my first serious counter project I am trying to keep
things simple, hence It Will Not Be State Of The Art. Maybe
a not-too-difficult hobby level counter will be of interest
to some, so I'd thought I'd post here...
The architecture in a couple of bulletpoints:
- fpga based as much as possible to keep the parts
- coarse counters running at max 200 MHz for now
- interpolation is done using TDC's. The TDC's look
suspiciously much like tapped delay lines and are
implemented inside the fpga, using mainly the carry chains.
- 10000 continuous time stamps per second
- 500 ps timestamp resolution. And with resolution I
mean the smallest resolvable thingy (related to bin size),
not precision nor accuracy.
500 ps single-shot resolution is what you probably want to
say.
Something like that yes. :)
How will the input side work? How will you handle input
signals of various kinds? In particular sine of various
amplitudes and frequencies. Slew-rate can be a limiting
factor as white noise will convert into jitter if hitting a
straight comparator. Choice of trigger point can be done to
achieve lowest jitter, so just AC-blocking and trigger on
the 0V may not be the best solution if shape is not well
known. Noise of input stage comes into play.
I am glad you asked. :) This is still one big To Be Determined at this point.
As you say, the choice of trigger point has a large impact on jitter. Do you have any suggestions on how to achieve this? Either for the situation where the signal shape is well known or not so well known.
...
The timestamps are transmitted over usb to the pc for
number crunching. The idea is to do some curve fitting to
get a frequency estimate, computate Allan Deviation, and do
the obligatory plots. With regard to Allan Deviation, as
long as I make sure the measurements have zero dead time, I
can compute Allan Deviation using the raw time stamps,
right?
Yes. Make sure time-stamps has a format such that software
can do time-wrapping extension.
--- On Thu, 1/6/11, Magnus Danielson <magnus@rubidium.dyndns.org> wrote:
> From: Magnus Danielson <magnus@rubidium.dyndns.org>
> Subject: Re: [time-nuts] No State Of The Art Counter
> To: "Discussion of precise time and frequency measurement" <time-nuts@febo.com>
> Date: Thursday, January 6, 2011, 10:05 PM
> On 01/06/2011 08:02 PM, Tijd Dingen
> wrote:
> > To whom it may concerns,
> >
> > Currently I am building a DIY frequency counter. Since
> this is my first serious counter project I am trying to keep
> things simple, hence It Will Not Be State Of The Art. Maybe
> a not-too-difficult hobby level counter will be of interest
> to some, so I'd thought I'd post here...
> >
> > The architecture in a couple of bulletpoints:
> > - fpga based as much as possible to keep the parts
> count down
> > - coarse counters running at max 200 MHz for now
> > - interpolation is done using TDC's. The TDC's look
> suspiciously much like tapped delay lines and are
> implemented inside the fpga, using mainly the carry chains.
> > - 10000 continuous time stamps per second
> > - 500 ps timestamp resolution. And with resolution I
> mean the smallest resolvable thingy (related to bin size),
> not precision nor accuracy.
>
> 500 ps single-shot resolution is what you probably want to
> say.
Something like that yes. :)
> How will the input side work? How will you handle input
> signals of various kinds? In particular sine of various
> amplitudes and frequencies. Slew-rate can be a limiting
> factor as white noise will convert into jitter if hitting a
> straight comparator. Choice of trigger point can be done to
> achieve lowest jitter, so just AC-blocking and trigger on
> the 0V may not be the best solution if shape is not well
> known. Noise of input stage comes into play.
I am glad you asked. :) This is still one big To Be Determined at this point.
As you say, the choice of trigger point has a large impact on jitter. Do you have any suggestions on how to achieve this? Either for the situation where the signal shape is well known or not so well known.
...
> > The timestamps are transmitted over usb to the pc for
> > number crunching. The idea is to do some curve fitting to
> > get a frequency estimate, computate Allan Deviation, and do
> > the obligatory plots. With regard to Allan Deviation, as
> > long as I make sure the measurements have zero dead time, I
> > can compute Allan Deviation using the raw time stamps,
> > right?
> Yes. Make sure time-stamps has a format such that software
> can do time-wrapping extension.
Will do!
regards,
Fred
RK
Rick Karlquist
Fri, Jan 7, 2011 10:53 PM
For prescaling, I'd suggest using the dividers in one of the Analog
Devices
PLL parts (ADF4xxx) instead of Hittite chips. Many of the AD parts can
still be purchased in packages with actual pins, and you can always get
them
in small quantities. They will also take a lot less power.
Warning. The AD parts have poorly specified low amplitude outputs.
If you can live with that, they're nice.
Rick Karlquist N6RK
>> For prescaling, I'd suggest using the dividers in one of the Analog
>> Devices
>> PLL parts (ADF4xxx) instead of Hittite chips. Many of the AD parts can
>> still be purchased in packages with actual pins, and you can always get
>> them
>> in small quantities. They will also take a lot less power.
Warning. The AD parts have poorly specified low amplitude outputs.
If you can live with that, they're nice.
Rick Karlquist N6RK
JM
John Miles
Fri, Jan 7, 2011 11:29 PM
For prescaling, I'd suggest using the dividers in one of the Analog
Devices
PLL parts (ADF4xxx) instead of Hittite chips. Many of the AD parts can
still be purchased in packages with actual pins, and you can always get
them
in small quantities. They will also take a lot less power.
Warning. The AD parts have poorly specified low amplitude outputs.
If you can live with that, they're nice.
Rick Karlquist N6RK
How so? The outputs are 3.3V CMOS, AFAIK...?
-- john, KE5FX
> >> For prescaling, I'd suggest using the dividers in one of the Analog
> >> Devices
> >> PLL parts (ADF4xxx) instead of Hittite chips. Many of the AD parts can
> >> still be purchased in packages with actual pins, and you can always get
> >> them
> >> in small quantities. They will also take a lot less power.
>
> Warning. The AD parts have poorly specified low amplitude outputs.
> If you can live with that, they're nice.
>
> Rick Karlquist N6RK
>
How so? The outputs are 3.3V CMOS, AFAIK...?
-- john, KE5FX
MD
Magnus Danielson
Sat, Jan 8, 2011 1:50 AM
On 07/01/11 23:45, Tijd Dingen wrote:
From: Magnus Danielsonmagnus@rubidium.dyndns.org
Subject: Re: [time-nuts] No State Of The Art Counter
To: "Discussion of precise time and frequency measurement"time-nuts@febo.com
Date: Thursday, January 6, 2011, 10:05 PM
On 01/06/2011 08:02 PM, Tijd Dingen
wrote:
To whom it may concerns,
Currently I am building a DIY frequency counter. Since
this is my first serious counter project I am trying to keep
things simple, hence It Will Not Be State Of The Art. Maybe
a not-too-difficult hobby level counter will be of interest
to some, so I'd thought I'd post here...
The architecture in a couple of bulletpoints:
- fpga based as much as possible to keep the parts
- coarse counters running at max 200 MHz for now
- interpolation is done using TDC's. The TDC's look
suspiciously much like tapped delay lines and are
implemented inside the fpga, using mainly the carry chains.
- 10000 continuous time stamps per second
- 500 ps timestamp resolution. And with resolution I
mean the smallest resolvable thingy (related to bin size),
not precision nor accuracy.
500 ps single-shot resolution is what you probably want to
say.
Something like that yes. :)
How will the input side work? How will you handle input
signals of various kinds? In particular sine of various
amplitudes and frequencies. Slew-rate can be a limiting
factor as white noise will convert into jitter if hitting a
straight comparator. Choice of trigger point can be done to
achieve lowest jitter, so just AC-blocking and trigger on
the 0V may not be the best solution if shape is not well
known. Noise of input stage comes into play.
I am glad you asked. :) This is still one big To Be Determined at this point.
As you say, the choice of trigger point has a large impact on jitter. Do you have any suggestions on how to achieve this? Either for the situation where the signal shape is well known or not so well known.
...
Well, you do have comparators and programmable trigger level. There is
no magic to that side. But do care about bandwidth. It might be needed
to actually not use a comparator up-front but rather let there be one or
two stages of gain, where the first one DC-shifts the signal with the
trigger level. This way you gain yourself to a higher slew-rate. This is
really what Collins-style ZCD do. The trick is to balance the gain and
noise-bandwidths such that you get optimum slew-rate bandwidth for
lowest added noise.
The timestamps are transmitted over usb to the pc for
number crunching. The idea is to do some curve fitting to
get a frequency estimate, computate Allan Deviation, and do
the obligatory plots. With regard to Allan Deviation, as
long as I make sure the measurements have zero dead time, I
can compute Allan Deviation using the raw time stamps,
right?
Yes. Make sure time-stamps has a format such that software
can do time-wrapping extension.
On 07/01/11 23:45, Tijd Dingen wrote:
>
>
> --- On Thu, 1/6/11, Magnus Danielson<magnus@rubidium.dyndns.org> wrote:
>
>> From: Magnus Danielson<magnus@rubidium.dyndns.org>
>> Subject: Re: [time-nuts] No State Of The Art Counter
>> To: "Discussion of precise time and frequency measurement"<time-nuts@febo.com>
>> Date: Thursday, January 6, 2011, 10:05 PM
>> On 01/06/2011 08:02 PM, Tijd Dingen
>> wrote:
>>> To whom it may concerns,
>>>
>>> Currently I am building a DIY frequency counter. Since
>> this is my first serious counter project I am trying to keep
>> things simple, hence It Will Not Be State Of The Art. Maybe
>> a not-too-difficult hobby level counter will be of interest
>> to some, so I'd thought I'd post here...
>>>
>>> The architecture in a couple of bulletpoints:
>>> - fpga based as much as possible to keep the parts
>> count down
>>> - coarse counters running at max 200 MHz for now
>>> - interpolation is done using TDC's. The TDC's look
>> suspiciously much like tapped delay lines and are
>> implemented inside the fpga, using mainly the carry chains.
>>> - 10000 continuous time stamps per second
>>> - 500 ps timestamp resolution. And with resolution I
>> mean the smallest resolvable thingy (related to bin size),
>> not precision nor accuracy.
>>
>> 500 ps single-shot resolution is what you probably want to
>> say.
>
>
> Something like that yes. :)
>
>
>> How will the input side work? How will you handle input
>> signals of various kinds? In particular sine of various
>> amplitudes and frequencies. Slew-rate can be a limiting
>> factor as white noise will convert into jitter if hitting a
>> straight comparator. Choice of trigger point can be done to
>> achieve lowest jitter, so just AC-blocking and trigger on
>> the 0V may not be the best solution if shape is not well
>> known. Noise of input stage comes into play.
>
>
> I am glad you asked. :) This is still one big To Be Determined at this point.
>
> As you say, the choice of trigger point has a large impact on jitter. Do you have any suggestions on how to achieve this? Either for the situation where the signal shape is well known or not so well known.
>
> ...
Well, you do have comparators and programmable trigger level. There is
no magic to that side. But do care about bandwidth. It might be needed
to actually not use a comparator up-front but rather let there be one or
two stages of gain, where the first one DC-shifts the signal with the
trigger level. This way you gain yourself to a higher slew-rate. This is
really what Collins-style ZCD do. The trick is to balance the gain and
noise-bandwidths such that you get optimum slew-rate bandwidth for
lowest added noise.
>>> The timestamps are transmitted over usb to the pc for
>>> number crunching. The idea is to do some curve fitting to
>>> get a frequency estimate, computate Allan Deviation, and do
>>> the obligatory plots. With regard to Allan Deviation, as
>>> long as I make sure the measurements have zero dead time, I
>>> can compute Allan Deviation using the raw time stamps,
>>> right?
>
>
>> Yes. Make sure time-stamps has a format such that software
>> can do time-wrapping extension.
>
> Will do!
>
> regards,
> Fred
>
>
>
>
>
> _______________________________________________
> time-nuts mailing list -- time-nuts@febo.com
> To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts
> and follow the instructions there.
TD
Tijd Dingen
Mon, Jan 10, 2011 9:42 PM
How will the input side work? How will you handle
signals of various kinds? In particular sine of
amplitudes and frequencies. Slew-rate can be a
factor as white noise will convert into jitter if
straight comparator. Choice of trigger point can
achieve lowest jitter, so just AC-blocking and
the 0V may not be the best solution if shape is
known. Noise of input stage comes into play.
I am glad you asked. :) This is still one big To Be
Determined at this point.
As you say, the choice of trigger point has a large
impact on jitter. Do you have any suggestions on how to
achieve this? Either for the situation where the signal
shape is well known or not so well known.
Well, you do have comparators and programmable trigger
level. There is
no magic to that side. But do care about bandwidth. It
might be needed
to actually not use a comparator up-front but rather let
there be one or
two stages of gain, where the first one DC-shifts the
signal with the
trigger level. This way you gain yourself to a higher
slew-rate. This is
really what Collins-style ZCD do. The trick is to balance
the gain and
noise-bandwidths such that you get optimum slew-rate
bandwidth for
lowest added noise.
Magnus, thanks for your reply. The Collin's style ZCD was a useful hint. Didn't know that one yet. I read up on it on Bruce's site. At least I think it is Bruce's site, what with the "/~bruce/" in the url. ;)
Especially the bit about the Generalised Collins Hard Limiter. Checked the paper, looks useful ... at a later date (it's on the list for rev 3 now). For now I have decided to keep the analog frontend as simple as I can get away with. Which in essence ranges from "nothing at all, straight up connect, better make sure what you connect is LVCMOS25/33 or LVPECL25/33" to "comparator + DAC, and just learn to live with the extra jitter until a later revision".
regards,
Fred
--- On Sat, 1/8/11, Magnus Danielson <magnus@rubidium.dyndns.org> wrote:
...
> >> How will the input side work? How will you handle
> input
> >> signals of various kinds? In particular sine of
> various
> >> amplitudes and frequencies. Slew-rate can be a
> limiting
> >> factor as white noise will convert into jitter if
> hitting a
> >> straight comparator. Choice of trigger point can
> be done to
> >> achieve lowest jitter, so just AC-blocking and
> trigger on
> >> the 0V may not be the best solution if shape is
> not well
> >> known. Noise of input stage comes into play.
> >
> >
> > I am glad you asked. :) This is still one big To Be
> Determined at this point.
> >
> > As you say, the choice of trigger point has a large
> impact on jitter. Do you have any suggestions on how to
> achieve this? Either for the situation where the signal
> shape is well known or not so well known.
> >
> > ...
>
> Well, you do have comparators and programmable trigger
> level. There is
> no magic to that side. But do care about bandwidth. It
> might be needed
> to actually not use a comparator up-front but rather let
> there be one or
> two stages of gain, where the first one DC-shifts the
> signal with the
> trigger level. This way you gain yourself to a higher
> slew-rate. This is
> really what Collins-style ZCD do. The trick is to balance
> the gain and
> noise-bandwidths such that you get optimum slew-rate
> bandwidth for
> lowest added noise.
Magnus, thanks for your reply. The Collin's style ZCD was a useful hint. Didn't know that one yet. I read up on it on Bruce's site. At least I think it is Bruce's site, what with the "/~bruce/" in the url. ;)
Especially the bit about the Generalised Collins Hard Limiter. Checked the paper, looks useful ... at a later date (it's on the list for rev 3 now). For now I have decided to keep the analog frontend as simple as I can get away with. Which in essence ranges from "nothing at all, straight up connect, better make sure what you connect is LVCMOS25/33 or LVPECL25/33" to "comparator + DAC, and just learn to live with the extra jitter until a later revision".
regards,
Fred
R
Rex
Mon, Jan 10, 2011 10:42 PM
On 1/10/2011 1:42 PM, Tijd Dingen wrote:
...
I read up on it on Bruce's site. At least I think it is Bruce's site, what with the "/~bruce/" in the url. ;)
...
regards,
Fred
I assume you mean: http://www.ko4bb.com/~bruce
That is not Bruce's site, rather DIDIER's site. Didier has been very
generous to make his website, http://www.ko4bb.com , available as a
repository for all sorts of time-nut related information. He has a large
test equipment manual page and a section on timing subjects, in addition
to other sections like ham radio.
Others here have provided similar web pages, like Tom VanBaak's
leapsecond.com.
Many also have provided us with some great software, like John Miles
http://www.thegleam.com/ke5fx/ , and Ulrich Bangert
http://www.ulrich-bangert.de/html/downloads.html .
And, of course, our host John Ackermann http://www.febo.com/ .
I just wanted to take this opportunity to thank these people and the
many others who make their time, knowledge and resources available to
support our time-nuttery.
-Rex
On 1/10/2011 1:42 PM, Tijd Dingen wrote:
> ...
> I read up on it on Bruce's site. At least I think it is Bruce's site, what with the "/~bruce/" in the url. ;)
>
> ...
>
> regards,
> Fred
>
>
I assume you mean: http://www.ko4bb.com/~bruce
That is not Bruce's site, rather DIDIER's site. Didier has been very
generous to make his website, http://www.ko4bb.com , available as a
repository for all sorts of time-nut related information. He has a large
test equipment manual page and a section on timing subjects, in addition
to other sections like ham radio.
Others here have provided similar web pages, like Tom VanBaak's
leapsecond.com.
Many also have provided us with some great software, like John Miles
http://www.thegleam.com/ke5fx/ , and Ulrich Bangert
http://www.ulrich-bangert.de/html/downloads.html .
And, of course, our host John Ackermann http://www.febo.com/ .
I just wanted to take this opportunity to thank these people and the
many others who make their time, knowledge and resources available to
support our time-nuttery.
-Rex
TD
Tijd Dingen
Mon, Jan 10, 2011 11:00 PM
That was indeed the site I meant. I stand corrected. :)
--- On Mon, 1/10/11, Rex rexa@sonic.net wrote:
From: Rex rexa@sonic.net
Subject: Re: [time-nuts] No State Of The Art Counter
To: "Discussion of precise time and frequency measurement" time-nuts@febo.com
Date: Monday, January 10, 2011, 10:42 PM
On 1/10/2011 1:42 PM, Tijd Dingen
wrote:
...
I read up on it on Bruce's site. At least I think it
is Bruce's site, what with the "/~bruce/" in the url. ;)
I assume you mean: http://www.ko4bb.com/~bruce
That is not Bruce's site, rather DIDIER's site. Didier has
been very generous to make his website, http://www.ko4bb.com , available as a repository for
all sorts of time-nut related information. He has a large
test equipment manual page and a section on timing subjects,
in addition to other sections like ham radio.
Others here have provided similar web pages, like Tom
VanBaak's leapsecond.com.
Many also have provided us with some great software, like
John Miles http://www.thegleam.com/ke5fx/ , and
Ulrich Bangert http://www.ulrich-bangert.de/html/downloads.html .
And, of course, our host John Ackermann http://www.febo.com/ .
I just wanted to take this opportunity to thank these
people and the many others who make their time, knowledge
and resources available to support our time-nuttery.
-Rex
time-nuts mailing list -- time-nuts@febo.com
To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts
and follow the instructions there.
That was indeed the site I meant. I stand corrected. :)
--- On Mon, 1/10/11, Rex <rexa@sonic.net> wrote:
> From: Rex <rexa@sonic.net>
> Subject: Re: [time-nuts] No State Of The Art Counter
> To: "Discussion of precise time and frequency measurement" <time-nuts@febo.com>
> Date: Monday, January 10, 2011, 10:42 PM
> On 1/10/2011 1:42 PM, Tijd Dingen
> wrote:
> > ...
> > I read up on it on Bruce's site. At least I think it
> is Bruce's site, what with the "/~bruce/" in the url. ;)
> >
> > ...
> >
> > regards,
> > Fred
> >
> >
>
> I assume you mean: http://www.ko4bb.com/~bruce
>
> That is not Bruce's site, rather DIDIER's site. Didier has
> been very generous to make his website, http://www.ko4bb.com , available as a repository for
> all sorts of time-nut related information. He has a large
> test equipment manual page and a section on timing subjects,
> in addition to other sections like ham radio.
>
> Others here have provided similar web pages, like Tom
> VanBaak's leapsecond.com.
>
> Many also have provided us with some great software, like
> John Miles http://www.thegleam.com/ke5fx/ , and
> Ulrich Bangert http://www.ulrich-bangert.de/html/downloads.html .
>
> And, of course, our host John Ackermann http://www.febo.com/ .
>
> I just wanted to take this opportunity to thank these
> people and the many others who make their time, knowledge
> and resources available to support our time-nuttery.
>
> -Rex
>
>
> _______________________________________________
> time-nuts mailing list -- time-nuts@febo.com
> To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts
> and follow the instructions there.
>
