High rate, high precision/accuracy time interval counter methods
Hi
Simple answer:
You are likely using an NPO cap and it’s not a big deal.
Bob
On May 8, 2016, at 9:49 PM, David davidwhess@gmail.com wrote:
How much will dielectric absorption in the capacitor affect the
accuracy of the result with such a high conversion rate? I am used to
dealing with it on much longer time scales and higher resolutions.
On Mon, 9 May 2016 01:08:05 +0200, you wrote:
Am 08.05.2016 um 21:53 schrieb Attila Kinali:
...
Maybe I was too short. We have control over the charging current source,
and when we switch it off, the status quo is kept. Then when the ADC is
done,
we can simply short the capacitor in the next clock/s to prepare for the
next cycle.
Attilla, we could discuss that on a sunny evening in Saarbrücken in a
beer garden if you like. The season starts :-)
regards, Gerhard
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On Sun, 8 May 2016 20:04:39 -0400
Bob Camp kb8tq@n1k.org wrote:
Attilla, we could discuss that on a sunny evening in Saarbrücken in a
beer garden if you like. The season starts :-)
… but how about the rest of us :)
How about a time-nuts conference/meet-up? :-)
And yes, i'm serious.
Attila Kinali
--
It is upon moral qualities that a society is ultimately founded. All
the prosperity and technological sophistication in the world is of no
use without that foundation.
-- Miss Matheson, The Diamond Age, Neil Stephenson
Since the GSPS sampling ADCs all appear to use an input buffer with relatively low value resistors between the differential inputs or connected to a midpoint bias voltage, some kind of high impedance buffer is needed between the TAC capacitor and the ADC input when using such ADCs. The highest clock frequency for capacitive input pipeline ADCs appears to be about 300MHz. A 1GSPS ADC relaxes the performance requirements of the TAC significantly making it easier to achieve 1ps or less noise.The trade off is that a discrete TAC may not be fast enough due to parasitic bond wire inductances etc. All monolithic TACs with 1ps resolution have been designed using standard IC processing.
Bruce
On Tuesday, 10 May 2016 12:14 AM, David <davidwhess@gmail.com> wrote:
Sure, and then we are back to a transition midpoint timing TDC. Or AC
couple it for a centroid timing TDC. These require a lot more
processing to generate a result compared to a time to amplitude
converter but with economical FPGAs and ARM microcontrollers, maybe
this does not matter.
I was just wondering about the speed limitations of a time to
amplitude based TDC. I am more comfortable with analog design than
using FPGAs.
On Mon, 9 May 2016 03:35:46 +0000 (UTC), you wrote:
Another option is to use a low pass filter to increase the transition times of the signal to be timestamped and use a pipelined ADC to sample the filter output.Perhaps something like the attached filter derived from:
http://bears.ucsb.edu/rad/pubs/conference/MTT_S_2004.pdf
May be effective in that it has near Gaussian response with relatively low out of band SWR.
Bruce
On Monday, 9 May 2016 3:01 PM, David davidwhess@gmail.com wrote:
How much will dielectric absorption in the capacitor affect the
accuracy of the result with such a high conversion rate? I am used to
dealing with it on much longer time scales and higher resolutions.
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In this case though we are talking about pushing the TAC resolution to
14 bits or maybe higher and that is about the level where dielectric
absorption starts to become a problem in all but the better film
capacitors. NP0 ceramics are perhaps more than an order of magnitude
worse than the best film dielectrics.
When I have built slow sample and hold circuits in the past, I did not
have a problem with dielectric absorption in NP0 capacitors however I
also did not push the resolution so far and the hold step was a larger
issue. For fast sample and hold circuits using diode bridges, the
sample capacitance is much smaller (or only parasitic) and resolution
was even lower so there was no problem there either. In slow
integrating converters, NP0 ceramics are poor at best.
15 to 50 Msps and 12+ bits is an area where I have not experimented so
I just wondered if the relatively poor dielectric absorption of NP0
would limit resolution. Testing it would be fun and low value
polyphenylene sulfide film capacitors are available as a benchmark.
I am a little dubious of getting a clean reset as well. :) This would
be one of those places where I would consider using a bipolar
transistor with the collector and emitter reversed unless a MOSFET or
closed loop reset was better.
On Mon, 9 May 2016 07:43:19 -0400, you wrote:
Hi
Simple answer:
You are likely using an NPO cap and its not a big deal.
Bob
On May 8, 2016, at 9:49 PM, David davidwhess@gmail.com wrote:
How much will dielectric absorption in the capacitor affect the
accuracy of the result with such a high conversion rate? I am used to
dealing with it on much longer time scales and higher resolutions.
Its probably easier/cheaper to construct a suitable filter for a GSPS ADC than to construct a TAC that is fast enough to suit an ADC with a GHz clock. Minimising the emitter to emitter inductance of a longtailed pair or equivalent is key to achieving a fast enough switching time for a suitable TAC. The reset switch also needs to have sub nanosecond turn on and turn off. Saturated bipolar switches are too slow. The classical dual diode clamped reset switch driven by a fast switching current source should work well if the parasitic interconnect inductances can be kept low enough.A custom IC is probably the only effective solution for such a TAC. The somewhat heroic measures employed in the Wavecrest counters is perhaps the limit of discrete construction techniques.
Bruce
On Tuesday, 10 May 2016 1:08 AM, Bruce Griffiths <bruce.griffiths@xtra.co.nz> wrote:
Since the GSPS sampling ADCs all appear to use an input buffer with relatively low value resistors between the differential inputs or connected to a midpoint bias voltage, some kind of high impedance buffer is needed between the TAC capacitor and the ADC input when using such ADCs. The highest clock frequency for capacitive input pipeline ADCs appears to be about 300MHz. A 1GSPS ADC relaxes the performance requirements of the TAC significantly making it easier to achieve 1ps or less noise.The trade off is that a discrete TAC may not be fast enough due to parasitic bond wire inductances etc. All monolithic TACs with 1ps resolution have been designed using standard IC processing.
Bruce
On Tuesday, 10 May 2016 12:14 AM, David davidwhess@gmail.com wrote:
Sure, and then we are back to a transition midpoint timing TDC. Or AC
couple it for a centroid timing TDC. These require a lot more
processing to generate a result compared to a time to amplitude
converter but with economical FPGAs and ARM microcontrollers, maybe
this does not matter.
I was just wondering about the speed limitations of a time to
amplitude based TDC. I am more comfortable with analog design than
using FPGAs.
On Mon, 9 May 2016 03:35:46 +0000 (UTC), you wrote:
Another option is to use a low pass filter to increase the transition times of the signal to be timestamped and use a pipelined ADC to sample the filter output.Perhaps something like the attached filter derived from:
http://bears.ucsb.edu/rad/pubs/conference/MTT_S_2004.pdf
May be effective in that it has near Gaussian response with relatively low out of band SWR.
Bruce
On Monday, 9 May 2016 3:01 PM, David davidwhess@gmail.com wrote:
How much will dielectric absorption in the capacitor affect the
accuracy of the result with such a high conversion rate? I am used to
dealing with it on much longer time scales and higher resolutions.
time-nuts mailing list -- time-nuts@febo.com
To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts
and follow the instructions there.
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and follow the instructions there.
Hoi Bruce,
On Mon, 9 May 2016 23:34:24 +0000 (UTC)
Bruce Griffiths bruce.griffiths@xtra.co.nz wrote:
Its probably easier/cheaper to construct a suitable filter for a GSPS ADC
than to construct a TAC that is fast enough to suit an ADC with a GHz clock.
Probably.
Minimising the emitter to emitter inductance of a longtailed pair or
equivalent is key to achieving a fast enough switching time for a suitable
TAC.
How does one minimize this inductance? The only way I am aware of is
to use a package with a pair of transistors with common emiter pin.
The somewhat heroic measures employed in the Wavecrest counters is
perhaps the limit of discrete construction techniques.
Are these heroic measures documented somewhere?
So far I have not even seen a block diagram of a Wavecrest counter,
much less a schematic.
Attila kinali
--
It is upon moral qualities that a society is ultimately founded. All
the prosperity and technological sophistication in the world is of no
use without that foundation.
-- Miss Matheson, The Diamond Age, Neil Stephenson
Hoi Attila
Yes, the only way to reduce emitter-emitter inductance is indeed to connect them on the die. Its even better if the current source transistor collector is also connected to the common emitter node of the long tailed pair on the die as this minimises the capacitance at this node.
Alternatively one can add a small series resistance to reduce the associated emitter circuit time constant as Wavecrest do.
The Wavecrest patent is somewhat detailed and complete with reasonably detailed circuit diagrams and explanatory text.
US6185509
US6194925 ***************
US6226231US4908784
Bruce
On Tuesday, 10 May 2016 9:17 PM, Attila Kinali <attila@kinali.ch> wrote:
Hoi Bruce,
On Mon, 9 May 2016 23:34:24 +0000 (UTC)
Bruce Griffiths bruce.griffiths@xtra.co.nz wrote:
Its probably easier/cheaper to construct a suitable filter for a GSPS ADC
than to construct a TAC that is fast enough to suit an ADC with a GHz clock.
Probably.
Minimising the emitter to emitter inductance of a longtailed pair or
equivalent is key to achieving a fast enough switching time for a suitable
TAC.
How does one minimize this inductance? The only way I am aware of is
to use a package with a pair of transistors with common emiter pin.
The somewhat heroic measures employed in the Wavecrest counters is
perhaps the limit of discrete construction techniques.
Are these heroic measures documented somewhere?
So far I have not even seen a block diagram of a Wavecrest counter,
much less a schematic.
Attila kinali
--
It is upon moral qualities that a society is ultimately founded. All
the prosperity and technological sophistication in the world is of no
use without that foundation.
-- Miss Matheson, The Diamond Age, Neil Stephenson
Am 09.05.2016 um 10:08 schrieb Magnus Danielson:
Hi,
On 05/08/2016 09:53 PM, Attila Kinali wrote:
True and not true. Yes, there are many ADCs that do high conversion
rates, but these are optimized for piplined applications where
conversion
happens at a constant rate. Ie they expect a constant conversion clock
with a constant rate. If you want to trigger conversion at an
arbitrary time,
you either have to build your own sampler or need to use one of the
non-pipelined ADCs whic are much slower (IIRC they stop around 5-10Msps
aka >100ns conversion time). Flash ADCs with direct access to the
sampling
circuitry are basically extinct.
You can let the ADC convert as a continuous process as long as you
filter out the samples you are interested in.
And, at least for the LTC2165, you could really use the encode clock to
read the result
of the capacitor immediately. All one would have to do is to flush the
pipeline with
5 or 6 clocks after the encode, with a cycle time not much faster than
10 ns and
not slower than 1 usec.
That seems not too hard to do but costs a differential mux in the encode
lines.
We then would not need to switch the current source, it could degenerate
to a
20V source with a resistor & safety clamps; that would be as linear as
it gets.
The reset level could be clamped by a Sky or Avago phemt, they can
swallow the
current easily, are blinding fast and do not drop a voltage for the base
current
over Re (from Gummel-Poon model). And an inverse transistor may have less
Re, but also less beta and therefore more base current.
I have already built a time stretcher and was restricted to spaceworthy
components;
those Intersil transistor arrays had the only acceptable PNPs. These
flatpacks are
huge, and the legs are endless; anything more complicated than a simple
current mirror would oscillate or would at least lurch to its
destination, and you
cannot simply damp it to death. Not funny.
Minimizing the E-E-inductance: The next best thing to an onchip-connection
might be abusing 2 Infineon SiGETs on the 2 sides of a thin board; they
are optimized
for low emitter inductance and have 2 emitter legs each. And their Early
voltage
is huge, so they are not impressed by the VCE changes of the current source.
(SiGe BFP650, 750 etc, available in a tiny package)
regards, Gerhard