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X440 Replay Trigger

SS
Schröder, Sebastian
Wed, Dec 11, 2024 1:09 PM

Dear USRP Users,

To characterize the radio, we want to start a recording on an external
device (R&S FSW) at the same time as the data from the X440 is played back
from the DRAM using a trigger.

Until now, the data from the DRAM has been played back continuously using
the replay block.

Our goal is to generate a trigger signal each time the replay is restarted
(starts from the beginning). Alternatively, we consider it equally valid to
restart playback each time a trigger signal is received.

As stated on the product page
<https://files.ettus.com/manual/page_usrp_x4xx.html#:~:text=The%20TRIG%20IN/
OUT%20port%20is%20not%20supported%20in%20default%20FPGA%20images> , the TRIG
port is not supported with the standard FPGA images. We would be grateful to
hear from anyone who has modified the FPGA image and used the TRIG port.

Alternatively, we would be interested to know if it is possible to use the
GPIO pins instead to achieve this result.

Best regards,

Sebastian Schröder

Fraunhofer Heinrich Hertz Institute HHI

Einsteinufer 37, 10587 Berlin, Germany

phone + 49 30 31002 877

email  mailto:sebastian.schroeder@hhi.fraunhofer.de
sebastian.schroeder@hhi.fraunhofer.de

http://www.hhi.fraunhofer.de/ www.hhi.fraunhofer.de |
https://twitter.com/FraunhoferHHI Twitter

Dear USRP Users, To characterize the radio, we want to start a recording on an external device (R&S FSW) at the same time as the data from the X440 is played back from the DRAM using a trigger. Until now, the data from the DRAM has been played back continuously using the replay block. Our goal is to generate a trigger signal each time the replay is restarted (starts from the beginning). Alternatively, we consider it equally valid to restart playback each time a trigger signal is received. As stated on the product page <https://files.ettus.com/manual/page_usrp_x4xx.html#:~:text=The%20TRIG%20IN/ OUT%20port%20is%20not%20supported%20in%20default%20FPGA%20images> , the TRIG port is not supported with the standard FPGA images. We would be grateful to hear from anyone who has modified the FPGA image and used the TRIG port. Alternatively, we would be interested to know if it is possible to use the GPIO pins instead to achieve this result. Best regards, Sebastian Schröder Fraunhofer Heinrich Hertz Institute HHI Einsteinufer 37, 10587 Berlin, Germany phone + 49 30 31002 877 email <mailto:sebastian.schroeder@hhi.fraunhofer.de> sebastian.schroeder@hhi.fraunhofer.de <http://www.hhi.fraunhofer.de/> www.hhi.fraunhofer.de | <https://twitter.com/FraunhoferHHI> Twitter