Bob I tried, (more than once), and now we are heading way off subject. I should of known better and learned by my past mistakers and stuck to the TPLL performance issues. Which TPLL graph or plot do you not understand? You need to ask the experts about the rest. ws ******************** [time-nuts] Advantages & Disadvantages of the TPLL Method Robert Benward rbenward at verizon.net Sat Jun 19 16:36:50 UTC 2010 Warren, I was responding to ke5fx comment "using a 12-bit, 480-Hz serial DAQ in place of the voltage-to-frequency converter in the diagram above". A DAQ is a multifaceted data acquisition system, where as in your annotated diagram you showed an ADC. I understand it's analog, but you said: "Say you have a nice logic gate with 1 ns delay" . So back to the analog loop, do you have an analysis that gets you from EFC to femtosecond stability? PLLs are notorious for phase noise, the phase noise actually representing the error term that brings the loop back into lock. For your second email: >You are now averaging the "repeatable" jitter? YES I was not questioning the procedure, I was questioning the conclusion; >Are you using a digital phase detector or a mixer as shown? Analog >Phase detector Why the digital analogy if it's all analog? >Do you have an analysis of the loop sensitivity/resolution? No >analysis, No limit it is analog I don't agree with you about the limit, and without an analysis or even a simple calculation, how do arrive at femtosecond lock? if there is no limit, why not a hundred times less? >Why do you say the results are repeatable in the short term vs the long >term? Long term includes other factors such as non random drift, not >just "random Noise" Maybe so, but using the "short term" , is not a license to better jitter figures by a factor of 100. Since you are not using digital, I don't know where this example came from or why it is relevant. > Is there not a lower limit to how much you can average? Depends or > everything, but not up to > 1 sec of averaging when the conditions are > made right I don't understand how you arrive at this conclusion For your last email: What attracted me to the TPLL question now was that you comment that you are maintaining a femtosecond lock. Please don't dumb it down for me. I may not understand all the statistical stuff, but I can understand an analysis. Bob ********************** ----- Original Message ----- From: "WarrenS" <warrensjmail-one at yahoo.com> To: "Discussion of precise time and frequency measurement" <time-nuts at febo.com> Sent: Saturday, June 19, 2010 3:27 AM Subject: Re: [time-nuts] Advantages & Disadvantages of the TPLL Method > Bob > >>> Don't know if I can explain it to you, I'm not so good at explaining, >>> I'll give it *ONE* try. >>> Example with some random picked numbers (JUST TO SHOW THE MAIN POINTS). > > I tried, > All information and test that are available on the TPLL is on JOHN'S > KE5FX > site or in past postings. > http://www.thegleam.com/ke5fx/tpll.htm > > One other thing I may not of made clear, The analog averaging thing does > not > help at low freq like at 1 PPS > The TPLL works great because it is at a high freq like 5 or 10 MHz. > DAQ == DataQ == ADC > >> I don't think 10ps is achievable under any dynamic conditions IMHO > OK, I don't really care, use whatever number you want, you'll still end up > below the Ref osc noise. > but > You may be surprised then by what the single shot "Aperture uncertainty" > specs are for the kind of devices that really care about this sort of > thing. > But then none of that really maters AT ALL, > because there is NO Digital anything in the simple TPLL before the ADC > where > a 10 Hz device would work fine for most. > I just gave you an example to try and answer your question on digital > logic > which was: >> How do you do fs when most digital logic has jitter several of orders of >> magnitude greater? > > ws > > *************************** > [time-nuts] Advantages & Disadvantages of the TPLL Method > Robert Benward rbenward at verizon.net > Sat Jun 19 03:18:05 UTC 2010 > > Warren, > Is there not a lower limit to how much you can average? Yes, it's the > sqrt > of the number of samples, but doesn't noise, > hardware, and other perturbations limit the usefulness of this method? > >> Then one can get repeatable results say 100 times better from cycle to >> cycle in the short term. >> so down to 10ps repeatable. > > Why do you say the results are repeatable in the short term vs the long > term? Isn't what you defined above > (repeatability) the opposite of jitter? Jitter I thought was cycle to > cycle > variation in prop delay. On 1ns prop > devices, I don't think 50-100ps jitter is unreasonable under the most > optimum conditions, the most careful circuit > layout, and constant repeatable inputs. I don't think 10ps is achievable > under any dynamic conditions IMHO. > >> One can average 1,000,000 readings of the 10 ps jitter >> If they are truly random, that can give you a 1e-3 improvement (square >> root of number of samples averaged) > > You are now averaging the "repeatable" jitter. > > KE5FX's website shows a diagram and a link to your diagram as well. Are > you > using a digital phase detector or a mixer > as shown? BTW, KE5FX refers to DAQ as your update to the design, where I > believe he meant an ADC. > > You have my curiosity peaked. Do you have an analysis of the loop > sensitivity/resolution? > > Bob > > > ----- Original Message ----- > From: "WarrenS" <warrensjmail-one at yahoo.com> > To: "Discussion of precise time and frequency measurement" <time-nuts at > febo.com> > Sent: Friday, June 18, 2010 6:49 PM > Subject: Re: [time-nuts] Advantages & Disadvantages of the TPLL Method > > >> Bob posted >>>can you explain it to me? >> >> Don't know, I'll give it ONE try. >> I'm not so good at explaining, but it is pretty basic if one does not >> start assuming that it can not be done at the >> start. >> It is mostly about averaging lots of those transitions, and the real >> trick >> is that it is not Digital. >> Analog has no lower limits except manly for Johnson noise type effects >> (mostly). >> >> Example with some random picked numbers. >> and assuming all analog that has no digital steps in it to limit >> resolution or add noise. >> >> Say you have a nice logic gate with 1 ns delay >> If you make it all nice and clean, and repeatable such as constant PS, >> rise time etc. >> Then one can get repeatable results say 100 times better from cycle to >> cycle in the short term. >> so down to 10ps repeatable. >> Now make things even more clean with no variations and assuming random >> noise. >> Now if one is doing this at 10 MHz and only cares about the average over >> 0.1 sec (10 Hz) >> One can average 1,000,000 readings of the 10 ps jitter >> If they are truly random, that can give you a 1e-3 improvement (square >> root of number of samples averaged) >> so now down to 10 fs of average jitter at 10 Hz for a 10 MHZ gate >> starting >> with a 1ns initial delay. >> >> OF course if Anything changes at all, it will drift much more than that, >> which may or may not mater much depending on >> what one is doing. >> If you only really care about the difference between any two consecutive >> 100 ms reading that are next to each other, >> as is (mostly) the case in ADEV, then not a big deal. >> >> IF it does matter or you want to do better, the next step is to do it all >> differential, so you are looking at only the >> different of two separate independent but equal circuits. Differential >> can >> give, say a 1000 to one or better >> improvement in drift due to common things such as temperature etc. >> >> If that helps explain the basics, good, if not you need to ask others to >> explain it better. >> >> And yes there all kinds of things that can & do go wrong and many ways to >> screw it up. >> so as easy as it sounds, it does take a bit of skill and art to do it. >> Especially when one realizes that you are measuring things << 0.001 in of >> distance change will have major effects on >> because of the speed of light. >> (approx 1ft /ns, 0.01 in/ps, 1 micron/4fs) >> >> >> Now if one starts out, not with a gate but a phase detector that is made >> for such things, and averages enough (but not >> to long) and is real careful, >> 1fs resolution is possible in the 100 Hz range with 10 MHz >> >> 10 MHz & 1fs at 100 Hz gives 1e-13 freq variation resolution at tau 10ms >> The simple BB TPLL is only getting about a tenth of that, (as shown on >> John's test plots) so it can be made much >> better with enough care, if anyone has a ref osc that needs it. >> But as I am always so quick to point out, the BB tester was not optimized >> for any one thing, It's performance was >> selected as a compromise for 'KISS' reasons. (KISS = Keep It Simple so >> the experts can understand.) >> >> please let me know on or off line if I'm wasting my time trying to >> explain >> this to the non "nut experts" without the >> help of the fancy math papers. >> >> ws >> >> ********************* >> [time-nuts] Advantages & Disadvantages of the TPLL Method >> Robert Benward rbenward at verizon.net >> Fri Jun 18 20:23:40 UTC 2010 >> Previous message: [time-nuts] Advantages & Disadvantages of the TPLL >> Method >> Messages sorted by: [ date ] [ thread ] [ subject ] [ author ] >> >> Warren, >> I'm a newbie, so can you explain it to me? Femto anything is something >> mostly reserved for a well equipped lab. How do you do it when most >> digital >> logic has jitter several of orders of magnitude greater? >> >> Bob >> >> *************************

Warren, All I wanted was an explanation of how you arrived at femtosecond timing. You gave me analogies instead. Since you cannot explain it, I ask anyone else on this listbot if they can put it in proper context for me. Thank you for your effort regardless. Bob ----- Original Message ----- From: WarrenS To: Discussion of precise time and frequency measurement Sent: Saturday, June 19, 2010 2:07 PM Subject: Re: [time-nuts] Advantages & Disadvantages of the TPLL Method Bob I tried, (more than once), and now we are heading way off subject. I should of known better and learned by my past mistakers and stuck to the TPLL performance issues. Which TPLL graph or plot do you not understand? You need to ask the experts about the rest. ws ******************** [time-nuts] Advantages & Disadvantages of the TPLL Method Robert Benward rbenward at verizon.net Sat Jun 19 16:36:50 UTC 2010 Warren, I was responding to ke5fx comment "using a 12-bit, 480-Hz serial DAQ in place of the voltage-to-frequency converter in the diagram above". A DAQ is a multifaceted data acquisition system, where as in your annotated diagram you showed an ADC. I understand it's analog, but you said: "Say you have a nice logic gate with 1 ns delay" . So back to the analog loop, do you have an analysis that gets you from EFC to femtosecond stability? PLLs are notorious for phase noise, the phase noise actually representing the error term that brings the loop back into lock. For your second email: >You are now averaging the "repeatable" jitter? YES I was not questioning the procedure, I was questioning the conclusion; >Are you using a digital phase detector or a mixer as shown? Analog >Phase detector Why the digital analogy if it's all analog? >Do you have an analysis of the loop sensitivity/resolution? No >analysis, No limit it is analog I don't agree with you about the limit, and without an analysis or even a simple calculation, how do arrive at femtosecond lock? if there is no limit, why not a hundred times less? >Why do you say the results are repeatable in the short term vs the long >term? Long term includes other factors such as non random drift, not >just "random Noise" Maybe so, but using the "short term" , is not a license to better jitter figures by a factor of 100. Since you are not using digital, I don't know where this example came from or why it is relevant. > Is there not a lower limit to how much you can average? Depends or > everything, but not up to > 1 sec of averaging when the conditions are > made right I don't understand how you arrive at this conclusion For your last email: What attracted me to the TPLL question now was that you comment that you are maintaining a femtosecond lock. Please don't dumb it down for me. I may not understand all the statistical stuff, but I can understand an analysis. Bob ********************** ----- Original Message ----- From: "WarrenS" <warrensjmail-one at yahoo.com> To: "Discussion of precise time and frequency measurement" <time-nuts at febo.com> Sent: Saturday, June 19, 2010 3:27 AM Subject: Re: [time-nuts] Advantages & Disadvantages of the TPLL Method > Bob > >>> Don't know if I can explain it to you, I'm not so good at explaining, >>> I'll give it *ONE* try. >>> Example with some random picked numbers (JUST TO SHOW THE MAIN POINTS). > > I tried, > All information and test that are available on the TPLL is on JOHN'S > KE5FX > site or in past postings. > http://www.thegleam.com/ke5fx/tpll.htm > > One other thing I may not of made clear, The analog averaging thing does > not > help at low freq like at 1 PPS > The TPLL works great because it is at a high freq like 5 or 10 MHz. > DAQ == DataQ == ADC > >> I don't think 10ps is achievable under any dynamic conditions IMHO > OK, I don't really care, use whatever number you want, you'll still end up > below the Ref osc noise. > but > You may be surprised then by what the single shot "Aperture uncertainty" > specs are for the kind of devices that really care about this sort of > thing. > But then none of that really maters AT ALL, > because there is NO Digital anything in the simple TPLL before the ADC > where > a 10 Hz device would work fine for most. > I just gave you an example to try and answer your question on digital > logic > which was: >> How do you do fs when most digital logic has jitter several of orders of >> magnitude greater? > > ws > > *************************** > [time-nuts] Advantages & Disadvantages of the TPLL Method > Robert Benward rbenward at verizon.net > Sat Jun 19 03:18:05 UTC 2010 > > Warren, > Is there not a lower limit to how much you can average? Yes, it's the > sqrt > of the number of samples, but doesn't noise, > hardware, and other perturbations limit the usefulness of this method? > >> Then one can get repeatable results say 100 times better from cycle to >> cycle in the short term. >> so down to 10ps repeatable. > > Why do you say the results are repeatable in the short term vs the long > term? Isn't what you defined above > (repeatability) the opposite of jitter? Jitter I thought was cycle to > cycle > variation in prop delay. On 1ns prop > devices, I don't think 50-100ps jitter is unreasonable under the most > optimum conditions, the most careful circuit > layout, and constant repeatable inputs. I don't think 10ps is achievable > under any dynamic conditions IMHO. > >> One can average 1,000,000 readings of the 10 ps jitter >> If they are truly random, that can give you a 1e-3 improvement (square >> root of number of samples averaged) > > You are now averaging the "repeatable" jitter. > > KE5FX's website shows a diagram and a link to your diagram as well. Are > you > using a digital phase detector or a mixer > as shown? BTW, KE5FX refers to DAQ as your update to the design, where I > believe he meant an ADC. > > You have my curiosity peaked. Do you have an analysis of the loop > sensitivity/resolution? > > Bob > > > ----- Original Message ----- > From: "WarrenS" <warrensjmail-one at yahoo.com> > To: "Discussion of precise time and frequency measurement" <time-nuts at > febo.com> > Sent: Friday, June 18, 2010 6:49 PM > Subject: Re: [time-nuts] Advantages & Disadvantages of the TPLL Method > > >> Bob posted >>>can you explain it to me? >> >> Don't know, I'll give it ONE try. >> I'm not so good at explaining, but it is pretty basic if one does not >> start assuming that it can not be done at the >> start. >> It is mostly about averaging lots of those transitions, and the real >> trick >> is that it is not Digital. >> Analog has no lower limits except manly for Johnson noise type effects >> (mostly). >> >> Example with some random picked numbers. >> and assuming all analog that has no digital steps in it to limit >> resolution or add noise. >> >> Say you have a nice logic gate with 1 ns delay >> If you make it all nice and clean, and repeatable such as constant PS, >> rise time etc. >> Then one can get repeatable results say 100 times better from cycle to >> cycle in the short term. >> so down to 10ps repeatable. >> Now make things even more clean with no variations and assuming random >> noise. >> Now if one is doing this at 10 MHz and only cares about the average over >> 0.1 sec (10 Hz) >> One can average 1,000,000 readings of the 10 ps jitter >> If they are truly random, that can give you a 1e-3 improvement (square >> root of number of samples averaged) >> so now down to 10 fs of average jitter at 10 Hz for a 10 MHZ gate >> starting >> with a 1ns initial delay. >> >> OF course if Anything changes at all, it will drift much more than that, >> which may or may not mater much depending on >> what one is doing. >> If you only really care about the difference between any two consecutive >> 100 ms reading that are next to each other, >> as is (mostly) the case in ADEV, then not a big deal. >> >> IF it does matter or you want to do better, the next step is to do it all >> differential, so you are looking at only the >> different of two separate independent but equal circuits. Differential >> can >> give, say a 1000 to one or better >> improvement in drift due to common things such as temperature etc. >> >> If that helps explain the basics, good, if not you need to ask others to >> explain it better. >> >> And yes there all kinds of things that can & do go wrong and many ways to >> screw it up. >> so as easy as it sounds, it does take a bit of skill and art to do it. >> Especially when one realizes that you are measuring things << 0.001 in of >> distance change will have major effects on >> because of the speed of light. >> (approx 1ft /ns, 0.01 in/ps, 1 micron/4fs) >> >> >> Now if one starts out, not with a gate but a phase detector that is made >> for such things, and averages enough (but not >> to long) and is real careful, >> 1fs resolution is possible in the 100 Hz range with 10 MHz >> >> 10 MHz & 1fs at 100 Hz gives 1e-13 freq variation resolution at tau 10ms >> The simple BB TPLL is only getting about a tenth of that, (as shown on >> John's test plots) so it can be made much >> better with enough care, if anyone has a ref osc that needs it. >> But as I am always so quick to point out, the BB tester was not optimized >> for any one thing, It's performance was >> selected as a compromise for 'KISS' reasons. (KISS = Keep It Simple so >> the experts can understand.) >> >> please let me know on or off line if I'm wasting my time trying to >> explain >> this to the non "nut experts" without the >> help of the fancy math papers. >> >> ws >> >> ********************* >> [time-nuts] Advantages & Disadvantages of the TPLL Method >> Robert Benward rbenward at verizon.net >> Fri Jun 18 20:23:40 UTC 2010 >> Previous message: [time-nuts] Advantages & Disadvantages of the TPLL >> Method >> Messages sorted by: [ date ] [ thread ] [ subject ] [ author ] >> >> Warren, >> I'm a newbie, so can you explain it to me? Femto anything is something >> mostly reserved for a well equipped lab. How do you do it when most >> digital >> logic has jitter several of orders of magnitude greater? >> >> Bob >> >> ************************* _______________________________________________ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.

Bob, I might shed some light on this topic, but my comments apply only to a few measurements made in my shop, not part of any PLL scheme. My intent was to determine the apparent noise floor of a Minicircuits SYPD-2 phase detector; a low offset, low conversion loss, DBM. The SYPD-2 IF port was terminated in 600 ohms in parallel with 0.1uF. The SYPD-2 was first characterized for DC output sensitivity with 10MHz @+7dBm on RF & 10.0001MHz @+7dBm on LO. At this drive level, the IF output is triangular & the "gain" was found to be 800 mV/Rad at 0VDC. I did not perform a tolerance analysis on this measurement & can only estimate the error at +/- 40mV/Rad. The 90 deg offset of the SYPD-2 was measured at < 500uV using +7dBm input power to both RF & LO ports. This measurement was performed to monitor the 90 deg offset DC for any obvious instability which might make lower level readings useless; the offset was stable to +/- 2uV over several minutes. Finally, the mixer was driven with +7dBm at both ports, but the LO port signal was delayed by a 90 deg hybrid splitter + a 500ps, DC to 2GHz, adjustable phase shifter. This configuration allows very fine (5K part settable resolution) adjustment to reach 0VDC output from the SYPD-2. The DC output stability was +/- 4uV/ minute after allowing an hour to reach thermal & mechanical equilibrium (& having no room temperature transients from my heating system). If the phase sensitivity can be assumed to scale down linearly, then 4uV resolution = 5uRad (80fs) @ 10MHz. With more care, or better equipment, <10fs resolution might be possible; but it will be difficult. Without knowing the noise type involved, it's unclear what benefit might be provided by averaging. More work needs to be done. Pete Rawson

Hi Pete, I calculated about 0.5uV/V for 10fs, so we are on the same page. I will need to read this several times for it to sink in, but I much appreciate the calculations and technical reply! Thanks! Bob ----- Original Message ----- From: Pete Rawson To: Discussion of precise time and frequency measurement Sent: Saturday, June 19, 2010 5:08 PM Subject: Re: [time-nuts] Advantages & Disadvantages of the TPLL Method Bob, I might shed some light on this topic, but my comments apply only to a few measurements made in my shop, not part of any PLL scheme. My intent was to determine the apparent noise floor of a Minicircuits SYPD-2 phase detector; a low offset, low conversion loss, DBM. The SYPD-2 IF port was terminated in 600 ohms in parallel with 0.1uF. The SYPD-2 was first characterized for DC output sensitivity with 10MHz @+7dBm on RF & 10.0001MHz @+7dBm on LO. At this drive level, the IF output is triangular & the "gain" was found to be 800 mV/Rad at 0VDC. I did not perform a tolerance analysis on this measurement & can only estimate the error at +/- 40mV/Rad. The 90 deg offset of the SYPD-2 was measured at < 500uV using +7dBm input power to both RF & LO ports. This measurement was performed to monitor the 90 deg offset DC for any obvious instability which might make lower level readings useless; the offset was stable to +/- 2uV over several minutes. Finally, the mixer was driven with +7dBm at both ports, but the LO port signal was delayed by a 90 deg hybrid splitter + a 500ps, DC to 2GHz, adjustable phase shifter. This configuration allows very fine (5K part settable resolution) adjustment to reach 0VDC output from the SYPD-2. The DC output stability was +/- 4uV/ minute after allowing an hour to reach thermal & mechanical equilibrium (& having no room temperature transients from my heating system). If the phase sensitivity can be assumed to scale down linearly, then 4uV resolution = 5uRad (80fs) @ 10MHz. With more care, or better equipment, <10fs resolution might be possible; but it will be difficult. Without knowing the noise type involved, it's unclear what benefit might be provided by averaging. More work needs to be done. Pete Rawson _______________________________________________ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.