On 22.08.22 00:24, John Sloan via time-nuts wrote:

Sparkfun's ZED-F9T breakout board interfaces look like a step up from
u-blox' RCB-F9T. However, my reason to use the RCB-F9T is simple: I've
had a bunch of these for years and don't want to throw them away. Also,
I need to feed the timepulse signals into a 50 Ohm load and the ZED-F9T
output pins are only rated for max. 5 mA [1]. Except for a 33 Ohm
resistor, the Sparkfun board routes both timepulse pins directly to the
SMA connectors [2]. I doubt that results in 50 Ohm source impedance
required to properly drive a high impedance load via a 50 Ohm
transmission line.

Have you had any issues with unmatched transmission line effects?

Best regards,
Carsten

[1]
https://content.u-blox.com/sites/default/files/ZED-F9T-00B_DataSheet_UBX-18053713.pdf#page=13
[2]
https://cdn.sparkfun.com/assets/6/c/2/5/b/SparkFun_GNSS_Timing-ZED-F9T_Schematic.pdf

Hi

The issue of terminating PPS signals and how to do it “right” has been debated
a lot on this list. A quick summary:

1. Some sort of termination is a really good idea. That termination should match
   the coax being used.

2. Some devices you might wish to drive already have a 50 ohm termination in
   them.

3. Most “modern” devices expect you to hit some sort of logic level with your
   drive signal. Is that 50% of 5V, 3.3V, 2.5V? Is it 0.8V TTL? Unfortunately each
   device and design is a bit different.

4. Will your “gizmo” that is looking for 3.3V ( or worse 2.5V) logic be ok with a
   5V peak signal? One would hope it will. There are some examples where the
   answer is no …

So what to do?

1. If you terminate with 50 ohms at the source, you can drive unterminated
   loads pretty well. Logic levels tend to line up. “Un-terminating” pieces of commercial
   gear simply to allow a terminated drive might not be a fun thing.

2. You can terminate both ends of the coax. This makes for the best match
   and the least ring on the line. It also means quite a bit of drive current. If you want
   5V logic levels, you need 10V drive. Good luck with your 3.3V unterminated device
   plugged into that output by accident ….

3. You can just terminate the load and drive the line from a low impedance / high
   current driver. Hitting a full ( so 90% ) logic swing this way at 5V into a load termination
   takes a pretty hefty driver. It also has to be fast and low jitter. Unfortunately this is
   what a lot of commercial gear seems to expect you to do.

If you have control over all the sources and loads, then picking a logic voltage is the
first step. Assuming there is a common ground, power all the sources with that
voltage. Make sure all the loads can tolerate / accept that voltage. Source only
50 ohm termination likely would be the rational way to set things up.

One can get “buffer” rated logic gates. Be sure to check things like the package
dissipation / current before buying a SOT-23 sized gizmo with 8 gates in it ( and
good luck mounting that BGA part … yikes …). Yes the duty cycle is low with
1 us pulses. Not so much with 50% duty cycle. Either way, package current may
limit you.

Parallel up as many gates as needed to hit the required current. If you are source
terminating a source load resistor goes in series with each gate output. With load
only termination, very small resistors are typically used (or no resistors at all). To hit
full 5V logic into load only terminated 50 ohms, you will use a lot of gates ….

Fun !!

Bob

Hi Folks,

read carefully ITU G.703 for 1PPS 50 Ohm or v.11 interface on RJ45 Con.

Cheers.

Uwe

Gesendet mit der mobilen Mail App

Am 22.08.22 um 20:47 schrieb Bob kb8tq via time-nuts

Hi Bob, Uwe,

thanks for the extensive summary and the ITU G.703 reference!

As an RF engineer by profession, I'm compelled to not (knowingly)
mistreat transmission lines :D

3.3V LVCMOS output level is determined by the ZED-F9T, so the
straightforward solution was to add a hand-solderable buffer opamp (TI
BUF602) that can drive +17 dBm into a 50 Ohm load. +17 dBm is already
quite a strong signal for most 50 Ohm RF measurement gear, so another
reason for being able to drive 50 Ohm loads is the option to use
standard 50 Ohm attenuators. Alternatively, the buffer amp enables 50
Ohm source termination to reliably drive 3.3V into high-impedance loads.
A good coincidence that the resulting output levels are ITU G.703
compliant :)

Best regards,
Carsten

On 22.08.22 21:00, Uwe via time-nuts wrote:

Hi

The BUF 602 needs dual 5V supplies to hit 3.3V logic levels. Running multiple supplies is a
bit of a PIA. Since this is a logic signal, cheap / fast / stable logic gates would seem to be
the obvious way to get the job done. 3.3V supply and away you go … The usual suspects
are all at least as fast and at least as low jitter as the BUF 602.

Bob

Hi Bob,

On 24.08.22 04:20, Bob kb8tq wrote:

I initially thought the same about the dual supplies. Fortunately, the
required average currents are fairly low (<100 mA to drive 5 loads at
3.3V and 50 Ohm each), so an inverting charge pump will do the job. The
SOT-23 LM2776 requires 3 capacitors in external circuitry, the WSON
LM27761 needs 4 caps and 2 resistors. I'm using the LM27761 on my
RCB-F9T adapter board. See my initial post for the layout.

Can you point me to any measurements or data sheets that characterize
the rise time, temperature dependency, and/or jitter/phase noise
performance of suitable logic gates? The fastest device families I could
find are 74LVC, 74AVC, and 74AUC. The 74HC often relied upon are
actually very slow [1]. I've discussed using 74-type components on the
EEVblog forum [2]. The 74s' typically large temperature coefficient
alone makes me reluctant to use them. The lack of jitter specs is an
exclusion criterion for me.

What are the "usual suspects" you refer to? I couldn't find any 74ish
device with official specs that can compete with the BUF602. As a
reasonably linear analog buffer, it shouldn't add any jitter on top of
its input voltage noise and has >45 dB PSRR up to 1 MHz. Its 8 V/ns slew
rate enables <0.5 ns rise times and it is straightforward to achieve 50
Ohm source termination. Improper source termination is also an exclusion
criterion for me.

In comparison, logic gates don't spec rise times <1 ns, have presumably
– correct me if I'm wrong – negligible PSRR, don't specify output
impedance, and require paralleling multiple outputs to drive 50 Ohm loads.

While the use of 74s may work for my application (whether sub-optimal or
not would be subject to tests), I'd rather err on the side of caution by
using parts that are explicitly specified for my use case.

Best regards,
Carsten

P.S.: If you're wondering why I need such high slew rates, my
application is phase synchronization of RF synthesizers like TI's
LMX2594. These require low phase noise, high slew rate reference and
sync signals. Again, I prefer to err on the side of caution by providing
the highest slew rate I can realize with reasonable effort.

[1] https://www.ti.com/lit/sg/sdyu001ab/sdyu001ab.pdf#page=2
[2]
https://www.eevblog.com/forum/projects/gpsdognssdo-stm32g4-u-blox-zed-f9t-tdc7200/msg4357849/#msg4357849

Carsten,
Forgive me asking an uninformed question
The LM27761 switches at 2MHz and is claimed to be low noise as the
switching is so fast but I expect it radiates at 2MHz and all harmonics.
You are looking for a 1ns rise time, probably to avoid diluting the 1PPS
accuracy, so the moment the 1PPS signal causes the line driver to switch
must be very well determined and stable
How do you avoid these harmonics to interfere with this switching?
I'm asking because I'm experiencing some problems with leakage of a
10MHz clock into the input of a fast comparator used for edge detection
and input to a counter, both on the same PCB, so I hope to learn from you.
Erik.

On 24-8-2022 9:19, Carsten Andrich via time-nuts wrote:

I don't see any explicit jitter specs on the BUF602 datasheet either.
Have you measured it?
How consistent is it from part to part?
The jitter of most CMOS families has been measured.
For example 74HC buffers typically have ~4ps jitter at room temperature.
Even this is much lower than the jitter of typical FPGAs when the effect of cross coupling from other clock domains such as internal oscillators etc are taken into account.
Faster logic families such as 74AC buffers (~ 1ps) have even lower jitter.
CMOS devices have a typical propagation delay tempco of around 0.4% of the delay per/C. FPGA gates have similar delay tempcos.
Neither the delay tempco nor the jitter is typically specified on CMOS device datasheets nor are they on the BUF602 datasheet so you have to measure them or leverage the results obtained by others.

Bruce

Am 2022-08-24 9:19, schrieb Carsten Andrich via time-nuts:

LMX2594 should not be very time pressing. I have published an
article in Dubus early this year on LMX2594 and everyone asked me then
where to buy.
I got 2 from Digikey last winter and since then the delivery time
was 1 year, and keeps being a year. :-(

Gerhard

On 24.08.22 10:05, Erik Kaashoek wrote:

Hi Erik,

don't hesitate to ask these kinds of questions, as explaining makes me
rethink my design*. Look at my schematic/layout while reading my
explanation.

As a charge pump, i.e., no inductor, radiated electro-magnetic
interferce (EMI) is presumably not an issue with the LM27761. That
leaves conducted EMI, for which it has an integrated linear
post-regulator to minimize output ripple, see Figs. 1 and 8 in the
datasheet [1]. In combination with the BUF602's >30 dB power supply
rejection ratio (PSRR) up to 10 MHz, the amount of switching noise on
the outputs is probably negligible.
*) I could probably add another ferrite bead (or one per BUF602) between
the LM27761 and the BUF602s to filter fast transients. The LM's 2 MHz
switching frequency is relatively low compared to, e.g., a 10 MHz
rectangular signal or transients of a 1 PPS output signal. So the charge
for switching low/high and potentially driving a 50 Ohm load during high
states must anyway come from the BUF602s' local decoupling caps.

To minimize switching noise from leaking back into the +5V net, I've
placed a ferrite bead at the LM27761's input. With decoupling caps
between the ferrite and any IC's supply pins, the decoupling capacitors
are the lowest impedance path for current transients. The ferrite bead
significantly increases the impedance of the board's power supply
compared to the local caps, so the ferrite kinda forces the transients
into the decoupling caps. I generally place ferrites for power supply
filtering and for anything analog or digital that may cause switching
transients. Unlike LC filters, which can oscillate, ferrite-based RC
filters are fairly safe. You "only" have to consider their added DC
resistance, power rating, and saturation effects with increasing current.

That could be a sign of insufficient or improper decoupling. Your 10 MHz
clock may somehow leak back into your power supply and the comparator
has insufficient PSRR to suppress the clocks transients on the power
supply. More decoupling and ferrite beads (one per digital IC) should
help in that case.

It may also be indicative of a general issue in your PCB design. Did you
ensure proper grounding, considering all signal return paths? On that
topic, I cannot recommend this video enough:
https://www.youtube.com/watch?v=ySuUZEjARPY
It is truly the single most important video on PCB design I've ever watched.

Best regards,
Carsten

[1] https://www.ti.com/lit/ds/symlink/lm27761.pdf

On 8/24/22 1:26 AM, Bruce Griffiths via time-nuts wrote:

This is true, as far as I know, of anything where you're pushing the
limits of performance.  Buy them, measure them, and use them if
acceptable.  And don't trust that buying the same part will still work
in the future.

Whether it's low jitter, low noise, prop delay, or whatever.

I could easily see Brand X 74AC having different characteristics than
Brand Y 74AC, while both meet the specs in the datasheets (which are
identical).

That's sort of the challenge faced by people who want to make one-off,
vs small volume, vs mass production.

For the first, you can use parts that happen to work that you happen to
have.  For the second, you can do a "buy and screen" sort of process.

For the latter, you either have to have "data sheet guarantees" (perhaps
as a specialty order from the MFR and they do screening)

In all cases you have to be willing to discontinue a product when the
parts you need are no longer available.

This is incredibly frustrating when you're trying to duplicate a
published state of the art design (even if "state of the art" was 1999)
and you have limited time (so you can't just buy a dozen different parts
and try them all)

By the way, don't forget the fast parts from Potato Semiconductor -
http://www.potatosemi.com/

Hi

The NC7SZ124 and 125 are typically one of the things used in this
sort of application. Their measured performance in various designs
is quite good. ( = they do not degrade the output of the module.

Bob

Hi Bruce,

On 24.08.22 10:26, Bruce Griffiths via time-nuts wrote:

Jitter isn't typically specified for analog amplifiers. At least the
ones I worked with never specified jitter. I'm not an expert on analog
RF components, but – like I wrote before – I'd assume that the opamp's
internal noise to be the only relevant source of additive jitter. Please
let me know if that assumption is wrong.

So far, I haven't measured anything. I've relied on the datasheet values
and the BUF602 seems to be the most promising (hand solderable) solution
for the job.

Could you kindly point me to such measurements? I'm curious.

These numbers (1~4 ps) are excellent in comparison to the ZED-F9T's
timepulse jitter. I estimate about 100 ps jitter when integrating John
Ackermann's phase noise measurement [1] from 1 Hz to 100 kHz. However,
my use case is not limited to the RCB-F9T adapter. I'm looking for a
generic solution that will also perform well with low noise OCXOs.

I'm taking a decent 100 MHz OCXO with the following phase noise as an
example: -100 dBc/Hz @ 10 Hz, -130 dBc/Hz @ 100 Hz, -160 dBc/Hz @ 1 kHz,
-170 dBc/Hz @ 10 kHz, 175 dBc/Hz @ >100 kHz.
That integrates to 18 fs from 12 kHz to 20 MHz (range is used for all
subsequent jitter values). The LMK1C110x weighs in at 8 fs typ. (20 fs
max.) for f = 156.25 MHz [2] and the LTC6957-3 has 90 fs typ. for f =
100 MHz [3].

The BUF602's input voltage noise of 4.8 nV/√Hz equals -153 dBm/Hz into
50 Ohm. Better, non hand solderable opamps exists, e.g., BUF802 with 2.3
nV/√Hz (-160 dBm/Hz) and AD8000 with 1.6 nV/√Hz (-163 dBm/Hz). Depending
on the OCXO's output level, the opamps' additive noise is barely
measurable over the OCXO's phase noise. Assuming +7 dBm OCXO output, the
AD8000 has a -170 dBc/Hz noise floor. Hence, I'd expect negligible
additive jitter.

With 1~4 ps jitter, the logic buffers are significantly worse. Also in
terms of temperature coefficient, the opamps are better off, because
their overall propagation delay is smaller. The BUF602 datasheet reports
300~600 ps group delay [4, Fig. 12].

Best regards,
Carsten

[1]
https://hamsci.org/sites/default/files/publications/2020_TAPR_DCC/N8UR_GPS_Evaluation_August2020.pdf#page=29
[2] https://www.ti.com/lit/ds/symlink/lmk1c1103.pdf#page=6
[3]
https://www.analog.com/media/en/technical-documentation/data-sheets/6957fb.pdf#page=9
[4] https://www.ti.com/lit/ds/symlink/buf602.pdf#page=9

On 8/24/22 04:26, Bruce Griffiths via time-nuts wrote:

This reminded me to mention -- crosstalk within the 74AC04 package is a
consideration.  In the TADD-2 PPS divider each output is derived from
three gates of a 74AC04 hex inverter, and can be independently set to a
different divisor rate (e.g., 1PPS, 100PPS, etc.).

Running two different rates into the same chip resulted in some
noticeable crosstalk from the faster to the slower rate.  Since
discovering that I've always made sure only one input clock goes into
each package.

John

On 24.08.22 16:39, Lux, Jim via time-nuts wrote:

Hi Jim,

IMHO, that's another reason to use opamp as buffers. At least with them
I'll be relying on characteristics, namely input voltage noise, that are
specified by the datasheet.

I also don't want to resort to trying out various different parts,
hoping/praying for excellent performance values not covered by the
specification, but instead start with an IC that is promising as per
what its datasheet actually specifies.

Best regards,
Carsten

Hi

The many ADEV plots posted on the list for the F9x series of parts put the 1 second
ADEV in the 100 to 200 ps range.

Given the dirt cheap nature of PCB’s these days, the idea making one application
more expensive / complex is generally not a great approach. Let JLPCB do up
enough of this or that and do a second board for a different application. Layout
wise, modern tools get things done very quickly.

But your -175 dbc phase noise is long gone ….

A discrete buffer typically is the right answer in most cases for low phase noise.

Bob

Hi Bob,

On 24.08.22 21:20, Bob kb8tq wrote:

You're right in terms of component and (automated) production cost, but
I'm also looking at it from an engineering cost perspective. Qualifying
multiple different solutions for a similar* problem is costly.
Hand-soldering the SMA connectors is already more expensive than the
price difference between logic buffers and buffer opamps. Add the
connectors on top and I'd doubt total savings on components would ever
amortize the added engineering costs for producing a few dozen devices.

*) By similar problem I mean low-noise buffering of arbitrary wideband
signals with 50 Ohm source impedance into both high impedance and 50 Ohm
loads. By arbitrary wideband signal I refer to any kind of typical
timing signal, whether it's a pulse (not necessarily only 1PPS) or
periodic rectangle at frequencies up to a few hundred MHz.

Unfortunately, yes. If phase noise is of most concern, then RF gain
blocks are obviously a better choice than buffer opamps. The HMC589 has
4 dB noise figure down to DC (allegedly) and even comes with phase noise
specs [1]. However, I doubt these gain blocks are a suitable choice if
3.3V CMOS logic levels are required.

Regardless, the LTC6957-3 I plan on using to convert a 100 MHz sine to
3.3V CMOS is considerably worse than the suggested buffer opamps in
terms of phase noise. Gotta spin off another thread on that ...

Are you referring to the same logic buffers that have 1~4 ps jitter? How
are these better than dedicated clock ICs with < 90 fs jitter specs and
a noise floor above my suggested opamps?

As always, I'd be grateful for references to exemplary components,
datasheets, designs, and measurement results.

Best regards,
Carsten

[1]
https://www.analog.com/media/en/technical-documentation/data-sheets/hmc589ast89e.pdf

Hi

If this is a commercial product that is targeted at a market then yes, the qualification
process gets into it. For a hobby use sort of design, it’s a pretty quick process and
“part of the fun”. If this is indeed a commercial design?

No, an amplifier made up of discrete transistors, resistors, capacitors and
the like.

Unfortunately that measurement data and the documentation that ran up to it is
property of my various employers over the last 50 years of designing OCXO’s and
GPSDO’s.

Bob

Hi Bob,

On 26.08.22 17:53, Bob kb8tq wrote:

It's a personal hobby project to deepen my circuit design experience and
to develop a proof-of-concept GNSSDO. However, I have a clear goal: A
100 MHz low phase noise mobile GNSSDO [1]. Nothing commercially
available satisfies my requirements.

Hence, the way is not the goal. For sth. as circumstantial as a low
noise 50 Ohm line driver, I don't want to spend time on experimenting
with and comparing different options (maybe "qualifying" was the wrong
term). For now, I prefer a straightforward one-fits-all solution with
decent performance (i.e., opamp like BUF602). If further down the road
that turns out to be insufficient, I can still delve into sth. discrete
like you suggested below.

Sorry, got it now.

Alright, thanks for sharing your experience.

Best regards,
Carsten

[1]
https://febo.com/pipermail/time-nuts_lists.febo.com/2022-April/105583.html