Multiple Time Interval Counters to measure Transients?
Hi fellow time nuts,
quite soon I'll have to come up with a clever idea to characterize a
few chips of a 130nm BiCMOS technology for transients. Unfortunately,
I'll have to look at something on the order of five dozen outputs per
chip, all at the same time.
If money and development time was no concern, I'd probably go with
roughly 250 Multi-GSample ADCs and sample all the outputs
simultaneously. Unfortunately, money is an issue (who would have
guessed? ;-P ), and I can't put several years into making this all
work. Not to speak of handling all the data generated...
The idea I have right now is employing something on the order of three
to five comparators per output, fed with different trigger levels. That
way I should be able to get some information on the transient shape as
well. But then I'll have to throw a few hundred Time Interval Counters
at the problem in order to get the information on the duration of the
transients. So in general, amplitude information comes from the
comparator trigger levels, time information from the TICs.
What I expect from the DUTs is transients in the range between 1 and
maybe 50 nanoseconds duration, but on some circuits they may be a lot
quicker as the bipolars are wicked fast (about 3-5 ps gate delay in
ECL inverters).
What do you guys think, would a truckload of TICs do the job? Maybe not
on the Bipolars, but at the plain CMOS this should do.
Any hints?
Best regards,
Florian
Hello,
On Sat, 8 Sep 2012, Florian Teply wrote:
(..) But then I'll have to throw a few hundred Time Interval Counters
at the problem in order to get the information on the duration of the
transients. So in general, amplitude information comes from the
comparator trigger levels, time information from the TICs.
What I expect from the DUTs is transients in the range between 1 and
maybe 50 nanoseconds duration, but on some circuits they may be a lot
quicker as the bipolars are wicked fast (about 3-5 ps gate delay in
ECL inverters).
What do you guys think, would a truckload of TICs do the job? Maybe not
on the Bipolars, but at the plain CMOS this should do.
It depends on how much precise you need the TICs (TDCs) to be. If it may
be around +-100ps..1ns, the solution is simple enough and some hundreds of
channels are feasible.
If you need units of ps, the challenge is big, IMHO. Currently, we are
testing our Time-to-Digit Converter within single FPGA, out last design
exhibited 7ps RMS of accuracy. In case you were interested, I expect
finishing of demo board during October. It would be more FPGA-resources
consuming, though.
Best regards,
Marek
Hello,
Am Sat, 8 Sep 2012 19:41:28 +0200 (CEST)
schrieb Marek Peca marek@duch.cz:
(..) But then I'll have to throw a few hundred Time Interval
Counters at the problem in order to get the information on the
duration of the transients. So in general, amplitude information
comes from the comparator trigger levels, time information from the
TICs.
What I expect from the DUTs is transients in the range between 1 and
maybe 50 nanoseconds duration, but on some circuits they may be a
lot quicker as the bipolars are wicked fast (about 3-5 ps gate
delay in ECL inverters).
What do you guys think, would a truckload of TICs do the job? Maybe
not on the Bipolars, but at the plain CMOS this should do.
It depends on how much precise you need the TICs (TDCs) to be. If it
may be around +-100ps..1ns, the solution is simple enough and some
hundreds of channels are feasible.
Well, for the CMOS stuff 100ps should do just fine. Of course, less
is better, but there's only so much one can reasonably do for so many
channels... Even a PICTIC should be able to do better than 500 ps for
a single channel. From what I've read, a few hundred units of HP5370
should solve the problem as well, but then there's only so much space...
If you need units of ps, the challenge is big, IMHO. Currently, we
are testing our Time-to-Digit Converter within single FPGA, out last
design exhibited 7ps RMS of accuracy. In case you were interested, I
expect finishing of demo board during October. It would be more
FPGA-resources consuming, though.
I'd be very much interested. 7ps to me seems to be even more than I'd
need for the CMOS stuff. Just out of curiosity: Does this work already
from 0ps on or is the minimum count higher than that? And what's the
limiting factor to accuracy you experience with your current design? Is
it actually the FPGA and its properties or something else?
Best regards,
Florian
Hello,
Well, for the CMOS stuff 100ps should do just fine. Of course, less
is better, but there's only so much one can reasonably do for so many
channels... Even a PICTIC should be able to do better than 500 ps for
a single channel. From what I've read, a few hundred units of HP5370
should solve the problem as well, but then there's only so much space...
Indeed, with such a precision, several dozens of TDCs could easily fit
into one FPGA chip. The task is to design clever data processing to handle
all the events.
We may be able to deliver such a custom product, but you have mentioned
your need to save as much money as possible -- it should have be made more
precise by means of technical specification to say more about time/price.
I'd be very much interested. 7ps to me seems to be even more than I'd
need for the CMOS stuff. Just out of curiosity: Does this work already
from 0ps on or is the minimum count higher than that? And what's the
limiting factor to accuracy you experience with your current design? Is
it actually the FPGA and its properties or something else?
Of course, the 7ps RMS is the jitter of the TDC. The measurement is
continuous w.r.t. reference clock, i.e. "0ps" is of course possible.
There is (almost) no other component than the FPGA. So, the limit is
indeed the FPGA itself, you may include its power-supplies and
comparators, as well.
However, you have been probably asking, how far from the limits imposed
bhy single FPGA cell's inherent jitter are we -- this is what I exactly
can not answer with certainty, but according to our indirect measurements,
best cells of the given FPGA exhibited estimated jitter about 1..3ps,
whereas our last complete design has overall 7ps RMS, under the assumption
of asynchronous measured signal. Under deterministic worst case, the
precision will drop to 21ps abs max. (Note: this last number may be a too
pesimistic value; stay tuned for newer revision after soldering recent
pcbs).
Feel free to ask more, if you were interested in testing our device.
Best regards,
Marek
Hi Florian,
On 09/08/2012 07:34 PM, Florian Teply wrote:
Hi fellow time nuts,
quite soon I'll have to come up with a clever idea to characterize a
few chips of a 130nm BiCMOS technology for transients. Unfortunately,
I'll have to look at something on the order of five dozen outputs per
chip, all at the same time.
If money and development time was no concern, I'd probably go with
roughly 250 Multi-GSample ADCs and sample all the outputs
simultaneously. Unfortunately, money is an issue (who would have
guessed? ;-P ), and I can't put several years into making this all
work. Not to speak of handling all the data generated...
The idea I have right now is employing something on the order of three
to five comparators per output, fed with different trigger levels. That
way I should be able to get some information on the transient shape as
well. But then I'll have to throw a few hundred Time Interval Counters
at the problem in order to get the information on the duration of the
transients. So in general, amplitude information comes from the
comparator trigger levels, time information from the TICs.
What I expect from the DUTs is transients in the range between 1 and
maybe 50 nanoseconds duration, but on some circuits they may be a lot
quicker as the bipolars are wicked fast (about 3-5 ps gate delay in
ECL inverters).
What do you guys think, would a truckload of TICs do the job? Maybe not
on the Bipolars, but at the plain CMOS this should do.
Any hints?
Check out Agilents Acquiris products, in particular the U1050A-002:
http://www.home.agilent.com/agilent/product.jspx?nid=-536902438.733419.00&cc=SE&lc=eng
You may also check out what GuideTech might have to offer that fits your
needs:
http://www.guidetech.com
There are others products, but none which to my knowledge fits your need
of channels.
Cheers,
Magnus
Am Sun, 09 Sep 2012 02:40:23 +0200
schrieb Magnus Danielson magnus@rubidium.dyndns.org:
Hi Florian,
On 09/08/2012 07:34 PM, Florian Teply wrote:
The idea I have right now is employing something on the order of
three to five comparators per output, fed with different trigger
levels. That way I should be able to get some information on the
transient shape as well. But then I'll have to throw a few hundred
Time Interval Counters at the problem in order to get the
information on the duration of the transients. So in general,
amplitude information comes from the comparator trigger levels,
time information from the TICs.
What I expect from the DUTs is transients in the range between 1 and
maybe 50 nanoseconds duration, but on some circuits they may be a
lot quicker as the bipolars are wicked fast (about 3-5 ps gate
delay in ECL inverters).
What do you guys think, would a truckload of TICs do the job? Maybe
not on the Bipolars, but at the plain CMOS this should do.
Any hints?
Check out Agilents Acquiris products, in particular the U1050A-002:
http://www.home.agilent.com/agilent/product.jspx?nid=-536902438.733419.00&cc=SE&lc=eng
This indeed is interesting. Now I can at least put some price tag to
the setup I had in mind. The unit you refer to goes for a bit more than
10k for 12 channels, so including a cPCI crate I'd have to find some
80k$ for all the outputs of a single chip. There I'll definitely have
to trade channels for measurement time, as I'll probably use 8 to 10
hours of beam time per run, going at 600-800 euros/h. So it'll be
definitely less expensive to just test one chip at a time...
Apart from that, I'll also check with ACAM in Germany as they have
ready-made chips that would do that, and 65 to 120 ps RMS accuracy is
okay for the CMOS stuff. Maybe they sell their chips for only a few
hundred euros each... ;-)
Best regards,
Florian
Hello,
Am Sat, 8 Sep 2012 21:56:45 +0200 (CEST)
schrieb Marek Peca marek@duch.cz:
Well, for the CMOS stuff 100ps should do just fine. Of course, less
is better, but there's only so much one can reasonably do for so
many channels... Even a PICTIC should be able to do better than 500
ps for a single channel. From what I've read, a few hundred units
of HP5370 should solve the problem as well, but then there's only
so much space...
Indeed, with such a precision, several dozens of TDCs could easily
fit into one FPGA chip. The task is to design clever data processing
to handle all the events.
We may be able to deliver such a custom product, but you have
mentioned your need to save as much money as possible -- it should
have be made more precise by means of technical specification to say
more about time/price.
Unfortunately, I don't have a more precise technical spec. I'm just
trying to find a viable solution to characterize a chip manufacturing
process with regard to Single-Event Transients. As this is supposed
to only be a side task for my PhD, I would prefer to use something that
already exists. On the other hand, until now I have no own budget, so
if I have to ask for money to buy stuff, it would better be something
that can be used for oher purposes as well.
I'd be very much interested. 7ps to me seems to be even more than
I'd need for the CMOS stuff. Just out of curiosity: Does this work
already from 0ps on or is the minimum count higher than that? And
what's the limiting factor to accuracy you experience with your
current design? Is it actually the FPGA and its properties or
something else?
Of course, the 7ps RMS is the jitter of the TDC. The measurement is
continuous w.r.t. reference clock, i.e. "0ps" is of course possible.
I was just asking because on some TDCs I read something about some 25
ps resolution and a counting range from 1 ns to 5 ms, which seems to
indicate a lower limit of 1 ns. I don't know enough about this to do
educated guesses on what this really might mean though, as I'm probably
not enough of a time-nut yet. Before, I only was interested in a
relatively stable frequency reference for amateur radio uses, so a
single GPSDO does the trick for me.
There is (almost) no other component than the FPGA. So, the limit is
indeed the FPGA itself, you may include its power-supplies and
comparators, as well.
However, you have been probably asking, how far from the limits
imposed bhy single FPGA cell's inherent jitter are we -- this is what
I exactly can not answer with certainty, but according to our
indirect measurements, best cells of the given FPGA exhibited
estimated jitter about 1..3ps, whereas our last complete design has
overall 7ps RMS, under the assumption of asynchronous measured
signal. Under deterministic worst case, the precision will drop to
21ps abs max. (Note: this last number may be a too pesimistic value;
stay tuned for newer revision after soldering recent pcbs).
What I had in mind here was the tradeoff between the flexibility of an
FPGA and the performance of a dedicated ASIC. Of course, this very much
depends on which optimizations were done and which technology is
targeted. In most applications, a 250 nm ASIC would have a hard time
beating an up-to-date FPGA from a 28 nm process, but in some areas it
might still have its benefits. I just wondered if this might be one of
the few places where ASICs still trump FPGAs. And of course, it'll make
a huge difference if you use a low-power CMOS or a top-of-the-notch
SiGe BiCMOS...
Being at a research fab, this question came to me quite naturally ;-)
Feel free to ask more, if you were interested in testing our device.
Depends on what you refer to by "testing". I'll be definitely the wrong
guy to ask for elaborated jitter measurements, especially in the
single-digit picosecond range. But if testing means giving your stuff a
shot to see if it fits my needs, I'm all in.
Hello,
just few quick comments:
Unfortunately, I don't have a more precise technical spec. I'm just
trying to find a viable solution to characterize a chip manufacturing
process with regard to Single-Event Transients. As this is supposed
to only be a side task for my PhD, I would prefer to use something that
already exists. On the other hand, until now I have no own budget, so
if I have to ask for money to buy stuff, it would better be something
that can be used for oher purposes as well.
Agreed. Fortunately, TDCs are usually made to be flexible enough, unless
they are tailored to a specific need of your application. What seemed to
me at the beginning of your requests.
What I had in mind here was the tradeoff between the flexibility of an
FPGA and the performance of a dedicated ASIC. Of course, this very much
depends on which optimizations were done and which technology is
targeted. (..)
In general, it's true. However, last year we have got results quite
comparable to ACAM's ASIC within relatively slow FPGA. We need to perform
more temperature-stability and aging tests to confirm the results.
Depends on what you refer to by "testing". I'll be definitely the wrong
guy to ask for elaborated jitter measurements, especially in the
single-digit picosecond range. But if testing means giving your stuff a
shot to see if it fits my needs, I'm all in.
The second option. I will let you know after assembling our eval boards.
They are 2-channel only.
Regards,
Marek
On Mon, Sep 10, 2012 at 9:08 PM, Florian Teply usenet@teply.info wrote:
Apart from that, I'll also check with ACAM in Germany as they have
ready-made chips that would do that, and 65 to 120 ps RMS accuracy is
okay for the CMOS stuff. Maybe they sell their chips for only a few
hundred euros each... ;-)
You might also want to have a look at this FMC with an ACAM chip on it:
http://www.ohwr.org/projects/fmc-tdc/wiki
It is made to work with this FMC carrier in PCIe format:
http://www.ohwr.org/projects/spec/wiki
The FMC carrier is a mature product. The TDC FMC is soon going to be
commercialized. The design is open, so it could give you some ideas in
any case.
We have also played with a TDC core in the FPGA
(http://www.ohwr.org/projects/tdc-core/wiki) using the same FMC
carrier with a simple digital I/O mezzanine
(http://www.ohwr.org/projects/fmc-dio-5chttla/wiki). This core is
based on delay lines inside the FPGA, using logic elements. In your
case it looks like a solution which would enable more channels in the
FPGA at the cost of some accuracy would probably suit better. You can
do this by e.g. sampling inputs with different phases of clocks in the
200 MHz realm, using the internal PLLs of FPGAs.
Cheers,
Javier