On eevblog there is a post about a lm399 voltage reference and a pwm
divider. Shouldn't be hard to find it.
Il 08/gen/2014 09:27 "Jan Fredriksson" jan@41hz.com ha scritto:

In message BBC0C14A893B4B5E8E434E94845E4FC1@athlon, "Ulrich Bangert" writes:

Once you get into that territory, the HP Journal articles on the
HP3458A ADC is mandatory reading:  The exact same issues are relevant
for a DAC.

--
Poul-Henning Kamp      | UNIX since Zilog Zeus 3.20
phk@FreeBSD.ORG        | TCP/IP since RFC 956
FreeBSD committer      | BSD since 4.3-tahoe
Never attribute to malice what can adequately be explained by incompetence.

Jan,

with standard PWM generated from a microcontroller the repetition rates of
the signal may get VERY slow with higher resolutions, making it difficult to
make a pure DC signal from. You should consider to use a Sigma-Delta DAC
which is very easy to program in a microcontroller. I have used AVR Megas
with software Sigma Delta DACs and precision analogue multiplexers to switch
between the reference and GND up to 20 bits of resolution. Worked fine!

Best regards
Ulrich

Also search for the General Purpose Power Supply Design thread on eevblog.
Lots of info there in reply #100 and above.

On Wed, Jan 8, 2014 at 7:32 AM, Poul-Henning Kamp phk@phk.freebsd.dkwrote:

On Wed, Jan 8, 2014 at 3:38 AM, Ulrich Bangert df6jb@ulrich-bangert.dewrote:

As a tradeoff if you're willing to not use hardware PWM, or if you're very
careful about controlling it anyway, you can look at how a very long phase
register works in a DDS ckt with a D/A having much fewer bits.  So it only
outputs a crude 8 bits or whatever but a very long register accumulates and
gradually corrects for error, at substantial phase noise cost of course.

Lets say in a FPGA you drive it at 100 MHz and have a 32 bit PWM counter.
That means a cycle time of 42 seconds which is awful (at half scale, how
many capacitor time constants is 21 seconds?  Or rephrased, assuming you
create a RC ckt with a 210 second RC constant, what, maybe a 2100 second
settling time aka a little less than a half hour?).  But what if you drove
a 16bit counter at 100 MHz?  Ah about half a millisecond.  Not so hard to
filter a 1 KHz square wave into 0.5 DC.  But at 3 bits/digit that 16 bit
PWM is scarcely 5 digits, eh just use a 6/7 digit KVD, simpler, more
accurate, more precise, and cheaper.  However there is a way around that...
you dither the PWM parameters on a regular controlled basis.  So all the
time you run 32768 counts, or half the time 32768 and half 32769 counts, or
all the time 32769 counts, tada at some considerable software complexity
you've built a 17 bit PWM D/A.  Now the 1 KHz "noise" that needs to be
turned into DC has a lot of phase noise, or theres a low freq component on
the spectrum analyzer.  So there's ways at the cost of some hardware and
software complexity to trade excellent repetition rates for truly awful
phase noise.

I've been fooling around with the idea of digitally generating wideband
white noise in a FPGA and then doing all the traditional DSP stuff to shift
the level up and down and even compensate at least partially for my
probably rotten "RF" to DC detector.  In the 80s (well, late 80s) I used an
8 bit sound blaster and generated .wav files (considerably slower than real
time, I'm sorry to say) that semi-controllably when fed thru a
rectifier-capacitor could make controllable DC voltages that varied to a
much smaller resolution than I had a multimeter to measure.  Of course the
settling time of the RC ckt was awful.  Also the non-linearity of the
rectifier probably vastly exceeded the possible precision of the digital
system.  I could have made some kind of synchronous controlled rectifier
using a fet that would have worked better, but...

Of course you've just turned a relatively simple DC voltage divider
problem, into a not too simple timing source problem AND a complicated
programming problem AND a complicated RF problem, so its more for "fun".

Jan Fredriksson jan@41hz.com writes:

Hi Jan,

There was a nice thread on sci.electronics.design "SMD TC??" about this.

https://groups.google.com/forum/#!searchin/sci.electronics.design/SMD$20TC$3F$3F

There were interesting ideas in there if you browse through the thread.

Some highlights quoted below, all due to James Arthur I think:

---====

Here's the basic PWM:

.........................
:
Vref >----///-----O    :
R1        \  :    R3
\  :    1M
O-----///---+-----> Vout
:          |
R2            :          --- Cf
0 >----///-----O    :          ---
:          |
........................:          |
===
Fig. 1

To me, 16 bits on the cheap is plenty cool.  But if the bar is doing
something extraordinary, like 1ppm, then it seems fair to use fancier
parts.

So, let's assume an FPGA and 100MHz clock rate, driving the switch.
The switch can either be the FPGA output, or an extra gate (or
paralleled gates).

We can get 1ppm modulating 100Hz in 10nS chunks.  Or 40Hz in 25nS
chunks, etc.  Whatever works out with our switch-speed.

Switch mis-match (R1-R2) produces a code-related error, maximized at
mid-scale.  With R3=1M, my algebra says <0.5ppm non-linearity from
switch mis-match requires |R1-R2| <= 1 ohm.  Y(A)MV.

Paralled gates, analog switches, or a BSS138 buffer stage could do
that.  I measured (characterized) some 74ACxx parts a ways back for
this.

Another, liberating possibility is to bootstrap the switches,
canceling most of their effective resistance:

     Vcomp >-------------.
                         |
                         |

......................... .-.
: | | R4
Vref >----///-----O    : | |
R1        \  : '-'
\  :  |    R3
O----+--///---+-----> Vout
:            |
R2            :            --- Cf
0 >----///-----O    :            ---
:            |
........................:            |
===
Fig. 2

If Vcomp is such that i(R4) = i(R3), the voltage drops (errors) across
R1 and R2 disappear.  This next version does that.

                        C1
        Vpwm >-----+----||----.
.-.  .-.           |          |

| |__| | =2Vrefp-p|          |
|        .-.
.....................V...      | |  R4
:  .  :      | | 100K, 1%
Vref >----///-----O .  :      '-'
R1    :  \  :      |    R3
:  \  :      |    100K, 1%
:    O---------+---///---+-----> Vout
:      :                  |
R2    :      :                  --- Cf
0V >----///-----O    :  R4=R3          ---
:      :                  |
.................:......:                  |
===
Fig. 3

C1-R4 re-create the same currents as flow in R3.  Effective switch
resistance (R1, R2) is lowered by about two orders of magnitude,
allowing us to reduce R3 and lower the output impedance.

Filtering the 100Hz PWM to 1ppm takes 14 time-constants = 140mS.

So, Fig. 3 is a working solution.  It's linear and accurate, but needs
a hi-z buffer amp and it's slow. A 16-bit version could be faster,
with lower-z output.  Or, splitting the DAC up into two sections
improves both those properties too.

                       C1

Vpwm(hi) >------------+---||---.
.-.  .-.          |        |
| |__| | =2Vrefp-p|        |
|        |
.....................V...    .-.
:  .  :    | | R4
Vref >----///-----O .  :    | |
R1    :  \  :    '-'
:  \  :    |    R3, 0.05%
:    O-------+--///---+---///--+-----> Vout
:      :                |    Rf    |
R2    :      :                |        --- Cf
0V >----///-----O    :  R4=R3        |        ---
:      :                |          |
.................:......:                |          |
|        ===
|
|
Vpwm(lo) >------------.                  |
|                  |
|                  |
.....................V...              .-.
:  .  :              | | R7
Vref >----///-----O .  :              | | = 1000 x R3, 0.05%
R5    :  \  :              '-'
:  \  :                |
:    O------------------'
:      :
R6    :      :
0V >----///-----O    :
:      :
.................:......:

    Fig. 4

If the upper and lower DACS cover 1,000:1 each, we could lower the
clock frequency to, say, 10MHz, pump it with a uC, and still have a
10kHz composite waveform that one-pole-filters to 1ppm in 14 * 100uS =
1.4mS.

The R7-R3 ratio is critical to absolute accuracy and monotonicity.
The top DAC divides Vref accurately into 1,000 parts, so a 1% error in
the R7-R3 divider ratio represents an error of 1 part in 100 of
1/1,000th, or 1 part in 100,000 overall.  0.05% ensures 0.5ppm.

Likewise, to ensure monotonicity to 1ppm, the lower DAC's contribution
of 1,000 lsb's cannot be off by >1 part (lsb) in those 1,000 lsb's, or
0.1%

The low DAC represents a small, code-related d.c. load on R1, R2 via
R7.  That needs to be either kept small, or compensated.

Back to the topic of this thread, the effect of T/C errors in the
divider resistors is reduced by the divider ratio, a factor of 1,000.

So, there's a stable, accurate, 1ppm PWM DAC made with non-critical
parts.

(more...)

--

John Devereux

"Ulrich Bangert" df6jb@ulrich-bangert.de writes:

Another approach is to combine a "coarse" and "fine" PWM (as Fluke do in
their calibrators I think).

--

John Devereux

Another cirquit that was not mentioned  up to now is the EDN Cirquit

http://edn.com/design/other/4326640/DC-accurate-32-bit-DAC-achieves-32-bit-resolution

The advantage is relative low effort and fast settling time. (for a PWM
solution)
Although you have to tweak the cirquit to get a fair linearity of around
2-3 ppm.
(The values in the article seem to be very optimistic to me).
Also the noise behaviour of my setup is not as good as would be a dual
dac version.

With best regards

Andreas

Am 08.01.2014 09:25, schrieb Jan Fredriksson: