To Bob kb8tq: Unfortunately, most of your post made very little sense. D-flops are noisy, and the higher you go in frequency, the noisier they are. This is clear from the schematic. Here is the schematic for a MC1670 D-flop: MC1670SC.PDF. Most of the noise is generated in the input SR latch. When the clock signal arrives, the input latch state is transferred to the output SR latch. Obviously, the sheer number of transistors involved is going to generate noise. Unfortunately, the D-flop is needed in every known synthesizer. Keeping this noise out of the signal is the goal of every designer. Stanford Research Systems is one company that has mastered the art. See https://www.thinksrs.com/products/siggen.html But you need to know how much noise is involved. That is where my new method can help. I am busy collecting parts - the HMC984LP4E's will arrive tomorrow, and I am looking for a pair of low noise VCXO's. I will have to regenerate test equipment that I haven't used in 5 decades to measure deadband, loop bandwidth, damping, crosstalk, jitter response, etc. I will also get a DBM to compare the results. I will also need ripple filters for the electronics. I have described this before in 2N3906G.PNG All this will take time - maybe months. But I have intended on making my own phase noise analyzer for a long time, and this will be an excellent way to get started. Along the way, there are plenty of other projects to attend to: a 4GHz to 8GHz low noise signal generator using YIG oscillators, a GPSDO to supply an accurate 10MHz reference, a new method of eliminating the sampling jitter in the 1PPS signal from the GPDSO, a low noise VCXO to supply a 10MHz reference from the 1PPS signal, an ultra stable signal generator to allow sampling of signals up to 150GHz, and so on. As there is little else to talk about, I will go silent while I am working on these projects. Bye Mike

HI We’re not building a synthesizer here. We are putting together a simple piece of test gear. The purpose of the test gear is to measure phase noise down into the -170 dbc / Hz range ….. Bob > On Jul 12, 2022, at 4:05 PM, Mike Monett via time-nuts <time-nuts@lists.febo.com> wrote: > > To Bob kb8tq: > > Unfortunately, most of your post made very little sense. D-flops are noisy, > and the higher you go in frequency, the noisier they are. This is clear > from the schematic. Here is the schematic for a MC1670 D-flop: MC1670SC.PDF. > > Most of the noise is generated in the input SR latch. When the clock signal > arrives, the input latch state is transferred to the output SR latch. > Obviously, the sheer number of transistors involved is going to generate > noise. > > Unfortunately, the D-flop is needed in every known synthesizer. Keeping > this noise out of the signal is the goal of every designer. Stanford > Research Systems is one company that has mastered the art. See > > https://www.thinksrs.com/products/siggen.html > > But you need to know how much noise is involved. That is where my new > method can help. I am busy collecting parts - the HMC984LP4E's will arrive > tomorrow, and I am looking for a pair of low noise VCXO's. > > I will have to regenerate test equipment that I haven't used in 5 decades > to measure deadband, loop bandwidth, damping, crosstalk, jitter response, > etc. I will also get a DBM to compare the results. > > I will also need ripple filters for the electronics. I have described this > before in 2N3906G.PNG > > All this will take time - maybe months. But I have intended on making my > own phase noise analyzer for a long time, and this will be an excellent way > to get started. > > Along the way, there are plenty of other projects to attend to: a 4GHz to > 8GHz low noise signal generator using YIG oscillators, a GPSDO to supply an > accurate 10MHz reference, a new method of eliminating the sampling jitter > in the 1PPS signal from the GPDSO, a low noise VCXO to supply a 10MHz > reference from the 1PPS signal, an ultra stable signal generator to allow > sampling of signals up to 150GHz, and so on. > > As there is little else to talk about, I will go silent while I am working > on these projects. > > Bye > > Mike > <MC1670SC.PDF><2N3906G.PNG>_______________________________________________ > time-nuts mailing list -- time-nuts@lists.febo.com > To unsubscribe send an email to time-nuts-leave@lists.febo.com