It is essential to understand exactly how this system works in theory.
No amount of hand waving or protestations will make its problems go away
if you use inappropriate signal processing methods.

The tight PLL (or any other PLL) forces the VCO (VCOXO int this case) to
servo the fluctuations in the phase difference between the test
oscillator and the VCO to zero within the PLL bandwidth.

To recover the phase fluctuations (assuming linearity of the VCO
response to its voltage control input) the EFC voltage has to be integrated.
Leaving aside the problems of saturation with most (but not all)
integrators, the phase fluctuations at the output of the VCO can be
recovered (to within a scale factor) by sampling the integrator output
to produce a set of synthesized phase samples. Alternatively one can
calculate the first differences of the periodic sequence of phase
samples to produce a series of scaled frequency averages.

In practice integrator saturation can be avoided by one of the following
methods:

1. Using a precision voltage to frequency converter and a counter to
   form the integrator.
   This is how NIST used to do it.
   The VFC110 from TI appears suitable.
   Avoid using a synchronous VFC (eg AD652) as they suffer from injection
   locking effects:
   http://www.analog.com/static/imported-files/tutorials/MT-028.pdf
   However if one samples the VFC integrator output at the end of each
   integration the effect of injection locking can be corrected for.
   DVMs like the HP/Agilent 34401A use a variation of this technique.
   Another thing to be aware of is that a DVM may have a built in RC low
   pass filter between its input terminals and its ADC.
   The effect of this may be significant if the averaging time (integration
   period) is too short.

2. Use an integrating DVM to sample the EFC voltage.
   The DVM samples are equivalent (to within a scale factor) to a set of
   frequency average samples.
   However most (but not all) DVMs have a finite deadtime between
   successive integrations, where the internal integrator is rundown for
   example.
   If one uses an integrating DVM with finite deadtime then the calculated
   values of ADEV should be corrected using the bias functions tabulated in
   NBS special publication 140 and elsewhere:
   http://digicoll.manoa.hawaii.edu/techreports/PDF/NBS140.pdf

3. The PLL has a finite bandwidth so one can sample it at a sufficiently
   high rate (> 2X PLL bandwidth as the PLL isnt a brickwall filter) and
   calculate the required frequency averages from the sampled data. Unless
   a very high oversampling rate is used merely averaging the values of a
   fixed number of samples will be insufficiently accurate. Attempts to use
   an arbitrary low pass filter to average the samples will bias the
   results. The averaging filter must have a frequency response that is
   very close to the sinc response of an integrator with an integration
   period equal to the sample interval.
   However this method is the most expensive as a high resolution ADC
   capable of relatively high sampling rates (10x the PLL bandwidth??) is
   required.

It is also essential to have sufficient isolation between the unit under
test and the VCO to avoid significant mutual injection locking effects.
To a first approximation such injection locking affects the PLL
parameters so that the PLL loop parameters need to be measured whilst
the PLL is closed when isolation is insufficient.

If one uses one of the Minicircuits phase detectors rather than an
arbitrary mixer then the isolation between the phase detector inputs is
much higher (at low frequencies at least) than that for most mixers.
Depending on the reverse isolation of the output buffers of the
oscillators being compared this isolation may be sufficient to avoid an
appreciable change in the PLL parameters. If the isolation is
insufficient one then needs to use a suitable isolation amplifier
between the the output of each oscillator and the phase detector.
The phase noise of the isolation amplifier should be lower than that of
the reference VCO (VCOCXO in this case).
Suitable isolation amplifiers are readily available as are circuit
schematics for isolation amplifiers known to have low phase noise you
can build for youself.
Just building an isolation amplifier using fast opamps or cascaded MMICs
without verifying the resultant phase noise is counterproductive.

Bruce

WarrenS wrote:

Warren,

Yes, I think it's a good idea for a couple of people to try to
duplicate your results; either to validate the resolution and
features that you're claiming, or to locate or quantify the
limitations in your implementation. Either way it will be a
learning experience for you, and for the group.

To that end, would you be able this week to write a quick
word document or readme or web page with photo(s) of
your setup, schematic, parts list, specific make/model of
the equipment that you're using, etc. Since you say it is
a simple setup, I suspect a number of us would then be
able to dig in our parts bin and mimic your prototype
as close as possible and then objectively measure how
it works compared to other phase noise measurement
systems.

/tvb

Tom

Things will turn out much better to do it the other way around.
When I find out who is going to build/test it,
I'll do something special for them and their tool box.

ws

----- Original Message -----
From: "Tom Van Baak" tvb@LeapSecond.com

Bruce

Thanks for your response, as always you've give me plenty to think about.

Turns out to be too true.
After re-reading your last post several times,
I now finally understand what you are saying and why you are saying it.
It is because YOU do not yet understand how this method works.
I find that so unbelievable, that I had not considered that possibility.

Starting at the following line and pretty much everything after that,
although accurate statements,
THEY DO NOT APPLY to this method.

...

ws

----- Original Message -----
From: "Bruce Griffiths" bruce.griffiths@xtra.co.nz
To: "Discussion of precise time and frequency measurement"
time-nuts@febo.com
Sent: Wednesday, February 10, 2010 2:32 PM
Subject: Re: [time-nuts] Tight PLL Tester

WarrenS wrote:

Warren

You seem to be the only one who doesn't understand the theory.
I understand exactly how the method as implemented by NBS is intended to
work.
Your ad hoc assumptions about the details of the method are false.

You admit to not knowing how to calculate how your implementation
responds to different phase noise spectra and yet you confidently
proclaim there will be no problems in interpreting the results?

Bruce

Thanks to the persistence and comments of others,
I have marked up an old  NBS diagram to show, anyone that wants to learn,
how the Tight Phase lock method works to do its 'Magic'.
Although it can be very simple and cheap to build, It does take a certain
amount of low noise design skill to be able to throw a bunch of parts bin
things together and make it work as well as it is capable of.
I do believe this information is enough for a well qualified person to
duplicate or even better my results.
I'm happy to try and answer any specific questions.

also see word discription from:
Page 170 of 'NBS special publication 140' at:
http://digicoll.manoa.hawaii.edu/techreports/PDF/NBS140.pdf    81 meg, 473+
pages  (Takes a while to download)

For another block diagram and short description also see Figure 1.7 at:
http://tf.nist.gov/phase/Properties/one.htm#oneone

Have Fun
ws

****** edited **********

If one follows that diagram blindly one will encounter a few problems
with a 10MHz mixer/phase detector input frequency.

1. The PLL is a first order loop and the frequency of the OCXO being
   servoed to the oscillator under test has to be carefully adjusted to be
   close to that of the oscillator under test so that the phase detector
   operates in its linear region. A second order PLL may be a better choice.

2. The mixer IF port termination is far from optimum (see later NIST
   papers).
   The phase detector sensitivity is much lower than with a better IF
   termination network.
   A simple simulation (or test on an actual mixer/phase detector) will
   show this.

3. An off the shelf 750uH inductor will typically exhibit several series
   and parallel resonances in the 100kHz to 20MHz region.
   Thus there may still be significant RF at the input of the dc amplifier
   with 80dB gain.
   There will be a significant sum frequency (20MHz) component at the input
   to the LC filter.
   The dc amplifier following the filter will rectify any RF at its input.
   Amplifiers with FET input stages are less sensitive to RF.
   An inductor with no resonances below 20MHz is preferred.
   100uH inductors with a first SRF greater than 20MHz are available but
   from Germany.
   It is usually advisable to use an RC filter between the LC filter output
   and the amplifier input to reduce the RF amplitude seen by the dc amplifier.
   Another option is to use a cascaded set of passive RC filters instead of
   the LC filter, but this inevitably increases the noise.

4. One cannot substitute either a DVM or an oversampling ADC for the V
   to F converter and counter and produce a set of output samples that will
   necessarily allow one to calculate accurate values for ADEV without
   correcting for the fact that the system phase noise spectral response
   will differ from that when a VFC is used.

If the shape of the phase noise transfer functions differ from that when
a VFC is used, the computed frequency stability measures obtained will
not be ADEV, MDEV etc.

Bruce

WarrenS wrote:

ws said

Bruce said:

Then that one should not be BUILDING the TESTER from scratch.

The PLL Close loop BW is NOWHERE near the Osc freq. I agree that would cause
severe problems.
The PLL BW has to be high compared to the 1sec LP filter value they are
using.
What I have shown in the markup, is a 1K to 10 KHz PLL bandwidth which makes
a good typical value.
IT IS NOT CRITICAL,  just has to be high compared to the low pass filter.

The Phase detector is ALWAYS operating in its linear region, and NEVER off
by even a mv at its output.
The high bandwidth 10,000 gain amps between it and the ref osc will see to
that.

A first order works fine at this bandwidth, with NO freq control RCs in the
loop.
When done right, there is only the natural pole of freq to phase

Which is why I use a C R C R C for mine.
My R's are 49 ohm, Nothing magic about the value, just that with 100 ohms,
they added more Johnson noise.

If all that is wanted is a chart recorder output, You can use any DVM as
shown in the block.
As long as the oversamping ADC is fast compared to the Low pass 1 sec filter
used in their block
Then the system FREQ noise spectral response as recorded in the PC Log file
is just about totally determined by the Low pass filter
and NOT the freq response or type of ADC or VtoF converter used or its
update rate.

I think we're making progress, I didn't see any mention of the nonexistent
Phase recovering integrator this time.

thanks, it's always fun to read your comments
ws

----- Original Message -----
From: "Bruce Griffiths" bruce.griffiths@xtra.co.nz
To: "Discussion of precise time and frequency measurement"
time-nuts@febo.com
Sent: Thursday, February 11, 2010 4:02 PM
Subject: Re: [time-nuts] Tight PLL Tester

WarrenS wrote:

All such details are important, even the type of resistor and at high
frequencies the actual part no and manufacturer.
Component parasitics (capacitor inductance, capacitor esr, resistor
inductance, resistor shunt capacitance, etc)can be very important in RF
circuits.
Not all resistors (or capacitors) of the same style/size from different
manufacturers have the same parasitics.

It should always be present either explicitly or implicitly, to believe
otherwise is to misunderstand the relationship between average frequency
and phase differences.

Without an integrator or its equivalent (implicit or explicit) the phase
noise transfer function will differ from that of the NBS implementation.
One way to approximate a box car integrator is to average the output
samples in blocks of N samples where N is the number of samples in the
minimum vale of Tau.
The minimum value of Tau should be around half the RC low pass filter
cutoff frequency period (you need to read the Stein paper for details).
However the sampling rate has to be sufficiently high (well above the
Nyquist limit) to allow this without using WSK interpolation to estimate
the signal value between the samples.

Bruce