Andreas,

Thanks for sharing the details of your project.  Building one of these DACs (or the 20-bit DAC described in LT's AN86 app note) has been on my to-do list for a while.

I'm wondering what your reason was for taking the measurements this way.  My first thought would have been to set one of the PWMs to a constant value and then manipulate the other.  For example, comparing H = 0x8000, L = 0x8000 with H = 0x8001, L = 0x8000 to measure the effect of single-step changes in the high PWM.  Or, fixing H at 0x8000 and stepping the L value through a range of values (with a step size equal to whatever you think is measurable above the noise).

And, FWIW, this link explains measurement of INL/DNL for a converter (specifically an ADC, but seems to apply to a DAC if you reverse everything):

http://www.maxim-ic.com/app-notes/index.mvp/id/283

Based on this, it would seem like you're computing what they call "End-point INL".  What Bruce describes is called "Best straight-line INL" and is the recommended approach.

Randy.

Randy Scott wrote:

One should avoid both 0% and 100% PWM duty cycle as there are then no
switching transitions of the error integrator input switch.
Depending on the switching times for the input switch and the PWM cycle
time this may be a significant contribution to non linearity if either
100% or 0% duty cycles are included.
The useful range for the PWM duty cycle decreases as the PWM period
decreases as the input switch switching transients have to fully settle
before the switch state changes again.

This form of indirect DAC is somewhat analogous to a dual slope ADC.
It is possible to devise variants that are analogous to a multislope ADC.
These variants should be less sensitive to the effects of dielectric
absorption.

The major contributor to INL is the Ron mismatch of the error integrator
input switch when switching to ground or the reference.
However this doesn't affect the monotonicity of the DAC so this effect
is usually of little consequence in closed loop control systems.

Bruce

As Randy already noted I measure the "end point INL".
I find this more useful when calibrating the endpoints and
then compensating the INL error by some kind of error curve.
In my case the error curve will be calibrated not so frequently as
the end points.
The best fit INL would give in most cases only about half the
value of the end point INL. So the datasheet values look
better if the best fit INL is used.

In my case the largest noise source is from the LTC2400 ADC which
is my best measurement equipment. He has 0.3ppm = 1.5uV
rms noise which will give about 10uVpp noise. Measurement condition
in the datasheet is with 0V at the input. The LT1027 reference of the ADC
contributes about 3uVpp. So practically I have about 8-20uVpp noise
over the full 0..5V input range. The only way to get rid of this noise is
to average many values.

Good point: the opamp was not powered up so I have to check wether
I have measured the substrate diodes.

With best regards

Andreas

Hello randy:

This has something to do with how the two ranges are mixed. (not added).
I simply want to get exact voltage divider ratios (2:1, 4:1 and so on)
without knowing the exact gain for the two stages.
The resistors are cheap 0.1% 15ppm/K RC55Y-resistors.
I have 51R + 1Meg for PWM H + L as resistors .
Giving nearly 2 Bits of overlap related to PWMH.
The formula for the output voltage is as follows:

VREF * (PWMH * (1Meg + RDS,on) + PWML * 51R) / (1Meg + RDS,on + 51R) / 65536

each PWMH step has around 76uV whereas the  total PWML range is about 255uV.

so when putting PWMH = 0x8000 and having PWML = 0x0000 with VREF = 5000mV
I  get VREF/2 - 127,5 uV. = 2499.8725 mV.
With PWMH  = PWML = 0x8000 the output is exact VREF/2. (all calculated
without INL error)

I think the best method for me to generate exact divider ratios will be the
following.

• determine INL-error for PWMH = PWML.
• generate some correction formula for this INL term
• Output the nearest PWMH - value assuming PWMH = PWML
• correct the last microvolts (+/- 38uV) on PWML-value

Since with my measurement equipment I will neiter be able
to determine the exact (temperature dependent?) ratio of
PWMH to PWML nor to calculate any (sub uV) INL values for the
PWML-range I want to do only small corrections with the
PWML-value assuming that the PWML-range has no own INL error.

With best regards

Andreas

Andreas

Andreas Jahn wrote:

Bad idea if there are significant endpoint discontinuities as may be the
case with this DAC when using the relatively slow switching MAX4053A.
In most cases, one can just avoid the few (1-2) endpoint codes that are
significantly affected.

Nonlinearity in the error integrator CMRR may also be significant for
this DAC when using the LTC1151.
This can be avoided by using a variant wherein which all opamp inputs
are close to zero volts thus eliminating the effect of common mode
nonlinearity.
This either requires a more complex switching arrangement for the
sampling capacitor or adding an inverter to the error correction loop.
In this variant the DAC gain depends on the ratio of 2 resistors.

You aren't by chance using carbon cermet or thick film resistors in your
circuit?

These are the known sources of noise for the ADC and reference, leakage
between the DAC integrator summing junctions and the power supplies may
be an issue if you havent used guard rings or teflon standoffs or
equivalent techniques.

Bruce