The contents of the latest issue of: International Journal of Embedded and Real-Time Communication Systems (IJERTCS) Official Publication of the Information Resources Management Association Volume 3, Issue 1, January – March 2012 Published: Quarterly in Print and Electronically ISSN: 1947-3176 EISSN: 1947-3184 Published by IGI Publishing, Hershey-New York, USA www.igi-global.com/ijertcs Editor-in-Chief: Seppo Virtanen, University of Turku, Finland Special Theme Issue on Perspectives on Signal Processing Megatrends GUEST EDITORIAL PREFACE “Special Theme Issue on Perspectives on Signal Processing Megatrends “ Tapani Ahonen, Tampere University of Technology, Finland Seppo Virtanen, University of Turku, Finland To read the preface, click on the link below, and then click on "Preface" in the 1st Quarter issue. http://www.igi-global.com/journal/international-journal-embedded-real-time/1162 PAPER ONE Scheduling, Binding and Routing System for a Run-Time Reconfigurable Operator Based Multimedia Architecture Erwan Raffin, Caps-enterprise, France Christophe Wolinski, IRISA/University of Rennes 1, France François Charot, INRIA Rennes–Bretagne Atlantique, France Emmanuel Casseau, IRISA/University of Rennes 1, France Antoine Floc’h, INRIA Rennes–Bretagne Atlantique, France Krzysztof Kuchcinski, Lund University, Sweden Stéphane Chevobbe, CEA–LIST, France Stéphane Guyetant, CEA–LIST, France This article presents an integrated environment for application scheduling, binding and routing used for the run-time reconfigurable, operator based, ROMA multimedia architecture. The environment is very flexible and after a minor modification can support other reconfigurable architectures. Currently, it supports the architecture model composed of a bank of single (double) port memories, two communication networks (with different topologies) and a set of run-time functionally reconfigurable non-pipelined and pipelined operators. The main novelty of this work is simultaneous solving of the scheduling, binding and routing tasks. This frequently generates optimal results, which has been shown by extensive experiments using the constraint programming paradigm. In order to show flexibility of our environment, we have used it in this article for optimization of application scheduling, binding and routing (the case of the non-pipelined execution model) and for design space exploration (case of the pipelined execution model). To obtain a copy of the entire article, click on the link below. http://www.igi-global.com/article/scheduling-binding-routing-system-run/62990 To read a PDF sample of this article, please visit http://www.igi-global.com/viewtitlesample.aspx?id=62990 PAPER TWO Design and Implementation of a Low-Complexity Multiuser Vector Precoder Maitane Barrenechea, University of Mondragón, Spain Luis Barbero, Queen’s University Belfast, UK Mikel Mendicute, University of Mondragón, Spain John Thompson, University of Edinburgh, UK Precoding techniques are used in the downlink of multiuser multiple-input multiple-output (MIMO) systems in order to separate the information data streams aimed at scattered user terminals. Vector precoding (VP) is one of the most promising non-linear precoding schemes, which achieves a performance close to the optimum albeit impractical dirty paper coding (DPC) with a feasible complexity. This contribution presents a novel design for the hardware implementation of a high-throughput vector precoder based on the Fixed Sphere Encoder (FSE) algorithm. The proposed fixed-complexity scheme greatly reduces the complexity of the most intricate part of VP, namely the search for the perturbing signal in an infinite lattice. Additionally, an optimized reduced-complexity implementation is presented which considerably reduces the resource usage at the cost of a small performance loss. Provided simulation results show the better performance of the proposed vector precoder in comparison to other fixed-complexity approaches, such as the K-Best precoder, under similar complexity constraints. To obtain a copy of the entire article, click on the link below. http://www.igi-global.com/article/design-implementation-low-complexity-multiuser/62991 To read a PDF sample of this article, please visit http://www.igi-global.com/viewtitlesample.aspx?id=62991 PAPER THREE Classification of Dataflow Actors with Satisfiability and Abstract Interpretation Matthieu Wipliez, IETR/INSA, France Mickaël Raulet, IETR/INSA, France Dataflow programming has been used to describe signal processing applications for many years, traditionally with cyclo-static dataflow (CSDF) or synchronous dataflow (SDF) models that restrict expressive power in favor of compile-time analysis and predictability. More recently, dynamic dataflow is being used for the description of multimedia video standards as promoted by the RVC standard (ISO/IEC 23001:4). Dynamic dataflow is not restricted with respect to expressive power, but it does require runtime scheduling in the general case, which may be costly to perform on software. The authors presented in a previous paper a method to automatically classify actors of a dynamic dataflow program within more restrictive dataflow models when possible, along with a method to transform the actors classified as static to improve execution speed by reducing the number of FIFO accesses (Wipliez & Raulet, 2010). This paper presents an extension of the classification method using satisfiability solving, and details the precise semantics used for the abstract interpretation of actors. The extended classification is able to classify more actors than what could previously be achieved. To obtain a copy of the entire article, click on the link below. http://www.igi-global.com/article/classification-dataflow-actors-satisfiability-abstract/62992 To read a PDF sample of this article, please visit http://www.igi-global.com/viewtitlesample.aspx?id=62992 PAPER FOUR Deadlock Free Routing Algorithm for Minimizing Data Packet Transmission in Network on Chip K. Somasundaram, Amrita Vishwa Vidyapeetham, India, and University of Turku, Finland Juha Plosila, University of Turku and Academy of Finland, Finland Network on chip (NoC) has been proposed as a solution for addressing the design challenges of future high performance nanoscale architectures. In NoCs, the traditional routing schemes are routing packets through a single path or multiple paths from one source node to a destination node, minimizing the congestion in the routing architecture. Although these routing algorithms are moderately efficient, they are time dependent. To reduce overall data packet transmission time in the network, the authors consider a network with multiple sources and multiple destinations. Multi-dimensional routing problems appear naturally in several resource allocation problems, communication networks and wireless sensor networks. In this paper, the authors have constructed a deadlock-free multi-dimensional path routing algorithm for minimizing the congestion in NoC. To obtain a copy of the entire article, click on the link below. http://www.igi-global.com/article/deadlock-free-routing-algorithm-minimizing/62993 To read a PDF sample of this article, please visit http://www.igi-global.com/viewtitlesample.aspx?id=62993 ***************************************************** For full copies of the above articles, check for this issue of the International Journal of Embedded and Real-Time Communication Systems (IJERTCS) in your institution's library. This journal is also included in the IGI Global aggregated "InfoSci-Journals" database: http://www.igi-global.com/EResources/InfoSciJournals.aspx. ***************************************************** CALL FOR PAPERS Mission of IJERTCS: The mission of the International Journal of Embedded and Real-Time Communication Systems (IJERTCS) is to disseminate recent advancements and innovations in this interdisciplinary research area for field researchers, practitioners, scientists, academicians, students, and IT professionals. IJERTCS focuses on overcoming challenges involved in the rapid development of embedded communication systems towards feature-rich multimedia computers Coverage of IJERTCS: The International Journal of Embedded and Real-Time Communication Systems (IJERTCS) extensively covers research in the area of embedded and real-time communication systems. Within this field, topics to be discussed in the journal include (but are not limited to) the following: Asynchronous and synchronous circuit techniques Design methods Embedded networks (built-in networks in embedded communication devices) Emerging new topics Fault-tolerant hardware and software technologies Formal design and verification methods Hardware and software solutions for protocol processing Hardware and software solutions for real-time systems Hardware platforms and technologies Hardware/software co-design Modeling and verification methods On-chip communication in SoC and NoC OWA (open wireless architecture) Performance modeling Platform based design Real-time computing Reconfigurable systems Security issues and technologies Single-chip SDR (software defined radio) solutions Software design Testing techniques Interested authors should consult the journal's manuscript submission guidelines at www.igi-global.com/ijertcs All inquiries and submissions should be sent to: Editor-in-Chief: Seppo Virtanen at seppo.virtanen@utu.fi