Hello, I'm working with the USRP x410 and need to transmit from all four ports at 200MSPS using the RFNoC replay block. Is this possible with the existing block? When I tried to duplicate the block, I encountered errors with memory connections. What's the best way to properly replicate this block in the FPGA to achieve multi-port transmission? Thanks

  replay0:

    block_desc: 'replay.yml'

    parameters:

      NUM_PORTS: 4

      MEM_DATA_W: 64

      MEM_ADDR_W: 32

Hey,\ \ Have you tried using a single replay block?\ The replay block can be configured to have multiple ports that each can be connected the radio. For example the [x410_X4_200_rfnoc_image_core.yaml](https://github.com/EttusResearch/uhd/blob/master/fpga/usrp3/top/x400/x410_X4_200_rfnoc_image_core.yml) bitfile variant should contain a 4 port replay block: ```   replay0: ``` ```     block_desc: 'replay.yml' ``` ```     parameters: ``` ```       NUM_PORTS: 4 ``` ```       MEM_DATA_W: 64 ``` ```       MEM_ADDR_W: 32 ``` \ There is an example that shows how to do this called tx_waveforms.\ Maybe this part of the example could be helpful for you?\ [rfnoc_dram_tx()](https://github.com/EttusResearch/uhd/blob/master/host/examples/python/tx_waveforms.py#L79 "rfnoc_dram_tx()") This separates the dram into different regions for each channel, so you are restricted to 1/4th the size of the replay blocks DRAM for each channel.\ This would limits the length of the waveform that you can transmit.\ \ The RFNoC variant of the tx_waveforms python example uses an internal helper class that simplifies DRAM usage, called DramTransmitter that makes using the replay block a little easier as a data source for transmission using RFNoC.\ It is defined [here in dram_utils.py](https://github.com/EttusResearch/uhd/blob/master/host/python/uhd/usrp/dram_utils.py#L56 "here in dram_utils.py") \ Maybe this can already help you to implement what you need.\ \ Regarding your question about using multiple instances of the replay block: \ I am not sure if this is possible, as I have never tried it myself.\ It seems like the X410 has 2 different dram ports, called [\`dram0\`](https://github.com/EttusResearch/uhd/blob/master/host/include/uhd/rfnoc/core/x410_bsp.yml#L133) and [\`dram1\`](https://github.com/EttusResearch/uhd/blob/master/host/include/uhd/rfnoc/core/x410_bsp.yml#L139) that are defined in the x410_bsp.yml. If they internally correspond to separate dram instances, it might be possible to instantiate 2 replay blocks.\ \ If it works, you will probably have to specify each replay block to use its own dram port, [see the BSP connection section for an example.](https://github.com/EttusResearch/uhd/blob/master/fpga/usrp3/top/x400/x410_X4_200_rfnoc_image_core.yml#L138)\ \ Regards,\ Niels