Didier Juges wrote:

Didier

A much simpler/cheaper though less flexible solution to the phase jerk
measurement problem.

Construct a preloadable synchronous up counter using 4 74HC163's
(74HC160 or 74HC162 also OK but may be harder to obtain).
Clock this at 10KHz from the GPS receiver. Use a 74HC164 to synchronise
the PPS output to 10KHz (use a 74HC86 as a clock buffer so the correct
clock polarity can be easily selected). Use a 74HC00 to generate a pulse
one clock cycle wide from the shift register 7th and 8th stage outputs.
This pulse is used to load the counter chain with a suitable value
corresponding to the desired delay. A decoder and a deglitching flipflop
are used to generate a glitch free GATE signal for the HP5370. A 74AC04
can be configured as a suitable driver for the ARM input. Additional
logic ensures that the counter resets to zero and stops until the next
PPS pulse occurs.

Bruce

Didier Juges wrote:

Since the HP5370 arm input is high impedance(1 Megohm) and its input
range lies betwen -2V and +2V its desirable to drive it from a back
terminated source with an amplitude of 2V or less to avoid overdriving
(the comparators are better behaved if the input signal remains within
the specified range) the input and ensure that the pulse at the ARM is
relatively clean and reflection free. A suitable buffer can be built
using 3 74AC04 inverters as depicted below: The 74AC04 inverters load
currents are well within the specified limits even if the buffer output
is shorted to ground. Thus the driver should have a long service life.
ARM driver

Bruce

Dr Bruce Griffiths wrote:

The trigger levels on the 5370 are strange. The normal inputs have
trigger levels that can be adjusted between -1.5 and +0.6 V or something
like that.
I am not sure where that is coming from.
For the ARM input, if someone is going to drive it with long coax
cables, the best would be a 50 ohm termination right at the instrument's
input.
The schematic did not make it, but I believe I understand what you mean:
3 gates with common input, each output has a 150 ohm series resistor and
the outputs (far end of the resistors) are tied together, to provide a
good 50 ohm drive to the cable. A series capacitor would probably be
recommended to center the signal around ground (assuming it's 50% duty
cycle).

Didier

Didier Juges wrote:

Since the delay generator is clocked at 10kHz 4029B synchronous up/down
binary/decade counters should be satisfactory.
Since the edge speeds are relatively slow breadboarding will be somewhat
simpler and more reliable.

Bruce

Dr Bruce Griffiths wrote:

Here we go, I don't even need to design it :-)
I have used XOR gates before as buffers to make sure I could select the
right polarity of a signal.

Well, for now I think I will simply use the 10 kHz but with the loop
time constant set for 1 PPS, with an option to speed it up for initial
phase lock, just to check that everything is working. I do not believe
there is any practical benefit in using the 10 kHz output for any other
reason, at least as far as time keeping is concerned.

Thank you all for all your advice and suggestions. I have enough to get
in real trouble for the next few weeks now.
Seems like I am going to build some synchronous dividers, write some
software, and build a remote controlled switch box too...

As I think of it, another advantage of the HP5334 for such an experiment
if the absence of a noisy fan, always appreciated for something that is
going to run 24/7 for a while.

Thanks again.

Didier KO4BB

Bruce,

Thanks for the reminder. That was my intention. I was planning to use a
74HC74, and whatever dividers I can get my hands on. I am not looking
forward to daisy chain seven 7490s, so I will probably try something
else. With the D flip-flop, the dividers don't really matter, as long as
the delay is below 100nS.
I need to find the best way to go from the 10 MHz sinewave to the
divider, probably through an LM119 comparator with modest hysteresis.
The need for a low jitter divider is the same for the GPS disciplined
oscillator, so I should be able to reuse the divider for my frequency
standard.

Thanks

Didier

Dr Bruce Griffiths wrote:

Didier Juges wrote:

Didier

The trigger level limits are derived from the input amplifier and
trigger circuit characteristics for the START and STOP inputs.

The ARM input feeds directly (via a 1X FET buffer) to an  ECL comparator
((MC1651).
This comparator has an NPN longtailed pair input stage the
characteristics of which determines the usable input signal range.
Driving an amplifier or comparator input stage into saturation degrades
its timing characteristics somewhat.

Bruce

Didier Juges wrote:

Didier

You can use a set of cascaded 74HC4017 Johnson counters to divide 10MHz
down to 1 Hz as long as you use a 2 stage (74AC74??) resynchroniser to
reduce the PPS jitter and reduce the effective propagation delay. With
an extra gate or 2 this will even work for a 5MHz input. It is not
necessary to have a 50% duty cycle signal to drive the HP5370 allowing
more flexibility in the divider design. I have designed a circuit using
74HC4017's to do this with a 5MHz input. If you want I can send it to you.

Satisfactory drivers for the HP5370 START and STOP inputs can also be
built by using a 270 ohm resistor in series with an ACMOS gate or
flipflop output. This produces a swing of around 800mV into a 50 ohm
load which is more than sufficient. The load current ratings of the
driver device are not exceeded even if the load is shorted.

Bruce

Dr Bruce Griffiths wrote:

I understand that the levels are what they are due to the use of ECL
logic, I was wondering from a user's perspective, was the 5370 intended
to be used only with ECL logic circuits? I am surprised that they did
not design a trigger range that included at least the "old" normal TTL
levels 0 to 5V. TTL was very common when the 5370 was designed (it uses
a lot of it internally, not so much in the timing circuits though)

Didier

Didier Juges wrote:

Didier

If you use a comparator, the LM119 is a bit on the slow side, a more
modern lower power comparator such as an AD8561 or similar would be
preferable.
Failing this, an overdriven longtailed pair using 2N3904's or equivalent
devices is usually perfectly satisfactory when the input amplitude is
sufficiently large (>= 1V pp).

To discipline the oscillator using GPS you dont actually need to divide
its frequency all the way down to 1Hz. As long as the output frequency
of the divider is a multiple of 1Hz and its period exceeds the
combination of the GPS PPS jitter and the oscillator timing drift/wander
over the loop response time any convenient output frequency can be used.

With a 10MHz oscillator, dividing its output by 16 allows a timing
wander jitter tolerance of 1.6us this is probably a little tight in most
cases, dividing the 10MHz by 256 gives you a jitter/wander budget of
25.6us which should be more than adequate for a good oscillator and a
loop response time of 1000 sec or so.

Bruce